Abstract: A regulator system with dynamic droop including a regulator control network which is adapted to control regulation of an output voltage to a reference level, a DC droop network which provides a droop signal to modify the reference level based on output load according to a predetermined DC load line, and a dynamic droop network which adjusts the droop signal to delay recovery to the predetermined DC load line within an AC load line tolerance in response to a load transient. A transient reduction network may be included to reduce transient overshoot for load insertion or release depending upon duty cycle type. The dynamic droop network adjusts the droop signal to optimize utilization of an AC delay parameter while transitioning between an AC offset voltage allowance and the predetermined DC load line.

Abstract: A predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.

Abstract: A predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.

Abstract: A regulator system with dynamic droop including a regulator control network which is adapted to control regulation of an output voltage to a reference level, a DC droop network which provides a droop signal to modify the reference level based on output load according to a predetermined DC load line, and a dynamic droop network which adjusts the droop signal to delay recovery to the predetermined DC load line within an AC load line tolerance in response to a load transient. A transient reduction network may be included to reduce transient overshoot for load insertion or release depending upon duty cycle type. The dynamic droop network adjusts the droop signal to optimize utilization of an AC delay parameter while transitioning between an AC offset voltage allowance and the predetermined DC load line.

Abstract: An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.

Abstract: An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.

Abstract: A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

Abstract: A phase removal control system for a multiphase DC/DC converter including combination logic, disable logic, and a current detector. The multiphase DC/DC converter includes first and second output phase circuits and a controller providing first and second PWM signals for the first and second output phase circuits, respectively. The combination logic combines the second PWM signal with the first PWM signal when a phase enable signal is de-asserted and while a current detect signal indicates current above a predetermined minimum current level. The disable logic passes the second PWM signal to the second output phase circuit when the phase enable signal is asserted and blocks the second PWM signal from the second output phase circuit when the phase enable signal is de-asserted. The current detector has an input for sensing current through the second output phase circuit and an output providing the current detect signal indicative thereof.

Abstract: A droop amplifier circuit for a DC-DC regulator including an amplifier, at least one first resistive device, a second resistive device, a third resistive device, and a first capacitive device. Each first resistive device is coupled between an output inductor (phase node or current sense node) and the amplifier's non-inverting input. The first capacitive device is coupled between the regulator output and the amplifier's output. The second resistive device is coupled between the regulator output and the amplifier's inverting input. The third resistive device is coupled between the amplifier's inverting input and output. A second capacitive device may be coupled between the regulator output and the amplifier's non-inverting input. A fourth resistive device may be coupled in parallel with the second capacitive device. A relatively small, simple and low performing amplifier is sufficient. Circuit area and power are reduced, and low input offset voltage is more easily achieved.

Abstract: A phase activation control system for a multiphase DC/DC converter including an amplifier circuit and enable logic. The converter includes a first phase circuit providing a first PWM signal and has a reduce input for reducing duty cycle of the first PWM signal. The converter further includes a second phase circuit providing a second PWM signal and having an enable input and an increase input for increasing duty cycle of the second PWM signal. The amplifier circuit has an enable input, a current sense input for sensing output current of the converter and an output providing an adjust signal. The adjust signal is provided to the reduce input of the first phase circuit and to the increase input of the second phase circuit. The enable logic receives a phase enable signal and enables the amplifier circuit and the second phase circuit.

Abstract: A multiphase synthetic ripple voltage generator for a multiphase DC-DC regulator including a master clock circuit that generates a master clock signal, sequence logic and a ripple regulator for each phase. The DC-DC regulator includes multiple switching circuits, each responsive to a corresponding PWM signal to switch input voltages via a phase node through an output inductor to develop an output voltage. The sequence logic sets each PWM signal in sequential order based on the master clock signal. Each ripple generator includes a transconductance amplifier, a ripple capacitor and a comparator. The transconductance amplifier has an input coupled to a corresponding output inductor and an output coupled to a corresponding ripple capacitor. The comparator has a first input coupled to the ripple capacitor, a second input receiving an error voltage, and an output coupled to the sequence logic for resetting a corresponding PWM signal.

Abstract: A transconductance amplifier with multi-emitter structure for balancing current of a multi-phase regulator including multiple transistors, a bias current device, multiple current mirrors, and multiple current sources. Each transistor has first and second current terminals and a current control terminal receiving a corresponding one of multiple sense voltages. Each sense voltage is indicative of output inductor current of a corresponding phase of the multi-phase regulator. The bias current device is coupled to the first current terminal of each transistor. Each current mirror has an input coupled to a second current terminal of a corresponding transistor and an output coupled to a corresponding one of multiple correction nodes. Each current source is coupled to a corresponding one of multiple correction nodes. In this manner, each correction node provides a correction current for a corresponding phase of the regulator.

Abstract: A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

Abstract: A droop amplifier circuit for a DC-DC regulator including an amplifier, at least one first resistive device, a second resistive device, a third resistive device, and a first capacitive device. Each first resistive device is coupled between an output inductor (phase node or current sense node) and the amplifier's non-inverting input. The first capacitive device is coupled between the regulator output and the amplifier's output. The second resistive device is coupled between the regulator output and the amplifier's inverting input. The third resistive device is coupled between the amplifier's inverting input and output. A second capacitive device may be coupled between the regulator output and the amplifier's non-inverting input. A fourth resistive device may be coupled in parallel with the second capacitive device. A relatively small, simple and low performing amplifier is sufficient. Circuit area and power are reduced, and low input offset voltage is more easily achieved.

Abstract: A multiphase ripple voltage regulator generator employs a hysteretic comparator referenced to upper and lower voltage thresholds. The hysteretic comparator monitors a master ripple voltage waveform developed across a capacitor supplied with a current proportional to the difference between the output voltage and either the input voltage or ground. The output of the hysteretic comparator generates a master clock signal that is sequentially coupled to PWM latches, the states of which define the durations of respective components of the synthesized ripple voltage. A respective PWM latch has a first state initiated by a selected master clock signal and terminated by an associated phase voltage comparator that monitors a respective phase node voltage.

Abstract: A transconductance amplifier with multi-emitter structure for balancing current of a multi-phase regulator including multiple transistors, a bias current device, multiple current mirrors, and multiple current sources. Each transistor has first and second current terminals and a current control terminal receiving a corresponding one of multiple sense voltages. Each sense voltage is indicative of output inductor current of a corresponding phase of the multi-phase regulator. The bias current device is coupled to the first current terminal of each transistor. Each current mirror has an input coupled to a second current terminal of a corresponding transistor and an output coupled to a corresponding one of multiple correction nodes. Each current source is coupled to a corresponding one of multiple correction nodes. In this manner, each correction node provides a correction current for a corresponding phase of the regulator.

Abstract: A multiphase synthetic ripple voltage generator for a multiphase DC-DC regulator including a master clock circuit that generates a master clock signal, sequence logic and a ripple regulator for each phase. The DC-DC regulator includes multiple switching circuits, each responsive to a corresponding PWM signal to switch input voltages via a phase node through an output inductor to develop an output voltage. The sequence logic sets each PWM signal in sequential order based on the master clock signal. Each ripple generator includes a transconductance amplifier, a ripple capacitor and a comparator. The transconductance amplifier has an input coupled to a corresponding output inductor and an output coupled to a corresponding ripple capacitor. The comparator has a first input coupled to the ripple capacitor, a second input receiving an error voltage, and an output coupled to the sequence logic for resetting a corresponding PWM signal.

Abstract: A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

Abstract: A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

Abstract: A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.