Patents by Inventor Thomas Andre

Thomas Andre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9972373
    Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 15, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
  • Publication number: 20180122495
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Applicant: Everspin Technologies Inc.
    Inventors: Thomas ANDRE, Jon SLAUGHTER, Dimitri HOUSSAMEDDINE, Syed M. ALAM
  • Patent number: 9911481
    Abstract: A selection circuit and related access circuitry that can be used for column selection in spin-torque magnetic memory is disclosed. The selection circuit can be implemented with three transistors, all of which can be NMOS transistors, thereby reducing area requirements. The selection circuit includes drive transistor that can be autobooted based on the drive voltage applied across the drive transistor. A single control signal controls the state of the selection circuit, and the selection circuits can be nested to provide multiple levels of decoding or selection.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 6, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 9881695
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 30, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Patent number: 9870812
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 16, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Publication number: 20170364647
    Abstract: A system and method generates a rule set. The method being performed by a rule generating device includes receiving a plurality of previously generated reports where each of the previously generated reports includes respective analysis content of a respective image. The method includes generating a candidate rule based upon the analysis content where the candidate rule is configured to increase a quality assurance of future reports. The method includes generating a respective score for each candidate rule based upon the candidate rule and the previously generated reports. The method includes including the candidate rule into the rule set when the score is above a predetermined threshold.
    Type: Application
    Filed: December 18, 2015
    Publication date: December 21, 2017
    Inventors: MERLIJN SEVENSTER, THOMAS ANDRE FORSBERG
  • Patent number: 9847116
    Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 19, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre
  • Publication number: 20170337959
    Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventor: Thomas ANDRE
  • Publication number: 20170315920
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Application
    Filed: April 28, 2016
    Publication date: November 2, 2017
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
  • Publication number: 20170301384
    Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM, Chitra SUBRAMANIAN
  • Publication number: 20170301173
    Abstract: A vending machine for selling or dispensing products or items to a user may include a container for storing and displaying the products. The container may have a transparent portion making the products visible from outside the container, and an aperture for removing one or more products by hand, wherein the aperture gives direct access to the products. An aperture access enabling device may selectively enable or prevent access through the aperture into the container. Finally, a recognition module for recognizing each of the products in the container, may include at least one module selected from the group consisting of: a camera based object recognition module, a weight recognition module, and an RFID recognition module. Also described are methods of operating the vending machine.
    Type: Application
    Filed: September 23, 2015
    Publication date: October 19, 2017
    Applicant: BUBBLY GROUP AS
    Inventors: Kim HINDSGAUL, Thomas André Eidal BLICHFELDT
  • Publication number: 20170263300
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas ANDRE, Dimitri HOUSSAMEDDINE, Syed M. ALAM, Jon SLAUGHTER, Chitra SUBRAMANIAN
  • Patent number: 9754652
    Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to either power or ground and, thereby determine the state associated with on the nonvolatile storage element.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 5, 2017
    Assignee: Everspin Technologies, Inc.
    Inventor: Thomas Andre
  • Patent number: 9740431
    Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
    Type: Grant
    Filed: July 17, 2016
    Date of Patent: August 22, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
  • Patent number: 9734884
    Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: August 15, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 9711566
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: August 6, 2016
    Date of Patent: July 18, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Patent number: 9697880
    Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.
    Type: Grant
    Filed: June 25, 2016
    Date of Patent: July 4, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
  • Patent number: 9691442
    Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 27, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Dietmar Gogl
  • Publication number: 20170178709
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Thomas Andre, Syed M. Alam
  • Patent number: 9679627
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 13, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian