Patents by Inventor Thomas Anthony Wassick
Thomas Anthony Wassick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11882645Abstract: A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.Type: GrantFiled: October 22, 2021Date of Patent: January 23, 2024Assignee: International Business Machines CorporationInventors: Sushumna Iruvanti, James Busby, Philipp K Buchling Rego, Steven Paul Ostrander, Thomas Anthony Wassick, William Santiago-Fernandez, Nihad Hadzic
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Patent number: 11756930Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.Type: GrantFiled: November 8, 2021Date of Patent: September 12, 2023Assignee: International Business Machines CorporationInventors: Charles Leon Arvin, Bhupender Singh, Shidong Li, Chris Muzzy, Thomas Anthony Wassick
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Publication number: 20230130104Abstract: A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.Type: ApplicationFiled: October 22, 2021Publication date: April 27, 2023Inventors: Sushumna Iruvanti, James Busby, Philipp K. Buchling Rego, Steven Paul Ostrander, Thomas Anthony Wassick, William Santiago-Fernandez, Nihad Hadzic
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Publication number: 20220059499Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Charles Leon Arvin, Bhupender Singh, Shidong Li, Chris Muzzy, Thomas Anthony Wassick
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Patent number: 11201136Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.Type: GrantFiled: March 10, 2020Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Charles Leon Arvin, Bhupender Singh, Shidong Li, Chris Muzzy, Thomas Anthony Wassick
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Publication number: 20210288025Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Inventors: Charles Leon Arvin, Bhupender Singh, Shidong Li, Chris Muzzy, Thomas Anthony Wassick
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Patent number: 11121101Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.Type: GrantFiled: January 30, 2020Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles Leon Arvin, Karen P. McLaughlin, Thomas Anthony Wassick, Brian W. Quinlan
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Publication number: 20210242146Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventors: Charles Leon Arvin, Karen P. McLaughlin, Thomas Anthony Wassick, Brian W. Quinlan
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Patent number: 10833051Abstract: Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.Type: GrantFiled: January 24, 2019Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Thomas Weiss, Thomas Anthony Wassick, Steve Ostrander
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Patent number: 10755404Abstract: Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.Type: GrantFiled: December 7, 2017Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung-Ching Lin, Thomas McCarroll Shaw, Peilin Song, Franco Stellari, Thomas Anthony Wassick
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Publication number: 20200243479Abstract: Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.Type: ApplicationFiled: January 24, 2019Publication date: July 30, 2020Inventors: Charles L. Arvin, Thomas Weiss, Thomas Anthony Wassick, Steve Ostrander
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Publication number: 20190180430Abstract: Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.Type: ApplicationFiled: December 7, 2017Publication date: June 13, 2019Inventors: Chung-Ching Lin, Thomas McCarroll Shaw, Peilin Song, Franco Stellari, Thomas Anthony Wassick
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Patent number: 8575007Abstract: The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.Type: GrantFiled: March 28, 2011Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Thomas Anthony Wassick
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Publication number: 20130249066Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.Type: ApplicationFiled: March 23, 2012Publication date: September 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: CHARLES L. ARVIN, KENNETH BIRD, CHARLES C. GOLDSMITH, SUNG K. KANG, MINHUA LU, CLARE JOHANNA MCCARTHY, ERIC DANIEL PERFECTO, SRINIVASA S.N. REDDY, KRYSTYNA WALERIA SEMKOW, THOMAS ANTHONY WASSICK
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Publication number: 20120248604Abstract: The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Thomas Anthony Wassick
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Patent number: 7875502Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.Type: GrantFiled: May 27, 2010Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Jon Alfred Casey, Ian D. Melville, David L. Questad, Wolfgang Sauter, Thomas Anthony Wassick
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Publication number: 20100233872Abstract: A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.Type: ApplicationFiled: May 27, 2010Publication date: September 16, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Brofman, Jon Alfred Casey, Ian D. Melville, David L. Questad, Wolfgang Sauter, Thomas Anthony Wassick
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Patent number: 7732932Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.Type: GrantFiled: August 3, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Jon Alfred Casey, Ian D. Melville, David L. Questad, Wolfgang Sauter, Thomas Anthony Wassick
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Publication number: 20090032909Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.Type: ApplicationFiled: August 3, 2007Publication date: February 5, 2009Inventors: Peter J. Brofman, Jon Alfred Casey, Ian D. Melville, David L. Questad, Wolfgang Sauter, Thomas Anthony Wassick
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Patent number: 7019402Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.Type: GrantFiled: October 17, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Leena Paivikki Buchwalter, Russell Alan Budd, Thomas Anthony Wassick