Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Abstract: A real-time Ethernet (RTE) protocol includes start-up frames originated by a master device for network initialization including a preamble, destination address (DA), source address (SA), a type field, and a status field including state information that indicates a current protocol state that the Ethernet network is in for the slave devices to translate for dynamically switching to one of a plurality of provided frame forwarding modes. The start-up frames include device Discovery frames at power up, Parameterization frames that distribute network parameters, and Time Synchronization frames including the master's time and unique assigned communication time slots for each slave device. After the initialization at least one data exchange frame is transmitted exclusive of SA and DA including a preamble that comprises a header that differentiates between master and slave, a type field, a status field excluding the current protocol state, and a data payload.