Patents by Inventor Thomas B. Phelps

Thomas B. Phelps has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9819317
    Abstract: An RF matrix switch has a first set of card slots at selected locations on the chassis and a second set of card slots at different selected locations on the chassis as well as input cards and output cards. The input cards, the output cards, the first set of card slots and the second set of card slots are all configured so that the input cards and the output cards fit into all of these slots. Reroute cards can be provided for any unused card slots. The RF matrix switch also may have an active power management system in which there is a power control switch connected to each amplifier that turns the amplifier off when the amplifier is not being used.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: November 14, 2017
    Assignee: Quintech Electronics & Communications, Inc.
    Inventors: Thomas B. Phelps, Nicholas J. Johnston
  • Publication number: 20160065136
    Abstract: An RF matrix switch has a first set of card slots at selected locations on the chassis and a second set of card slots at different selected locations on the chassis as well as input cards and output cards. The input cards, the output cards, the first set of card slots and the second set of card slots are all configured so that the input cards and the output cards fit into all of these slots. Reroute cards can be provided for any unused card slots. The RF matrix switch also may have an active power management system in which there is a power control switch connected to each amplifier that turns the amplifier off when the amplifier is not being used.
    Type: Application
    Filed: August 20, 2015
    Publication date: March 3, 2016
    Inventors: Thomas B. Phelps, Nicholas J. Johnston
  • Patent number: 4972105
    Abstract: A reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical "1" is written to the RAM cell for that connection and if no connection is desired, a "0" is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner.
    Type: Grant
    Filed: September 22, 1989
    Date of Patent: November 20, 1990
    Assignee: The U.S. Government as represented by the Director, National Security Agency
    Inventors: Dennis A. Burton, Wendy L. Goble, Robert D. Morelli, Thomas B. Phelps