Abstract: A method and system for improving the performance of a cache. The cache may include a tag entry that identifies the previously requested address by the processor whose data was not located in the cache. If the processor requests that address a second time, then there is a significant probability that the address will be accessed again. When the processor requests the address identified by the tag entry a second time, the cache is updated by inserting the data located at that address and evicting the data located in the least recently used entry. In this manner, data will not be evicted from the cache unless there is a significant probability that the data placed in the cache will likely be accessed again. Hence, data may not be evicted in the cache by the processor and replaced with data that will not be reused, such as in an interrupt routine.

Abstract: A method (and system) of improving performance of a multiprocessor system, includes proactively flushing and locking an arbitrarily-sized region of memory out of caches of the multiprocessor system.

Abstract: A connection assembly comprising a receptacle portion and a probe portion. The receptacle portion is suitable for attaching to an adapter card. The receptacle may include a cylindrical housing with a longitudinal axis oriented perpendicular to the plane of the card. The receptacle includes a set of contact structures that extend within the interior of the receptacle housing. The set of contact structures are embedded within an electrically insulating contact block and preferably define one or more lines of contact structures extending perpendicularly to the plane of the adapter card. Each contact structure is electrically connected to a corresponding cable or wire. The probe portion may include a probe cover and a probe body configured to be received within the probe cover. The probe cover preferably comprises first and second elements that are separated by a gap that extends parallel to the longitudinal axis of the receptacle.

Abstract: A personal digital assistant (PDA) which includes a body portion and a keyboard adapted to be coupled to the body portion. The keyboard is a standard keyboard size when in use. The keyboard is also foldable to act as a cover for the body portion. In a preferred embodiment, the keyboard attaches directly to the PDA and when not in use acts as a cover for the display of the PDA. When the keyboard is unfolded and the PDA is placed onto a flat surface, the user is able to input information using their familiar touch-typing skills with a full-size keyboard.

Abstract: A method (and system) of improving performance of a multiprocessor system, includes proactively flushing and locking an arbitrarily-sized region of memory out of caches of the multiprocessor system.

Abstract: A connection assembly comprising a receptacle portion and a probe portion. The receptacle portion is suitable for attaching to an adapter card. The receptacle may include a cylindrical housing with a longitudinal axis oriented perpendicular to the plane of the card. The receptacle includes a set of contact structures that extend within the interior of the receptacle housing. The set of contact structures are embedded within an electrically insulating contact block and preferably define one or more lines of contact structures extending perpendicularly to the plane of the adapter card. Each contact structure is electrically connected to a corresponding cable or wire. The probe portion may include a probe cover and a probe body configured to be received within the probe cover. The probe cover preferably comprises first and second elements that are separated by a gap that extends parallel to the longitudinal axis of the receptacle.

Abstract: A method and system in a superscalar data processing system are disclosed for the temporary designation and utilization of a plurality of physical registers as a stack. For each of the multiple instructions to be processed during a single clock cycle by the data processing system, a determination is made whether each of the instructions is a particular type of instruction. If a determination is made that an instruction is a particular type of instruction, a quantity of physical registers to be temporarily designated as a stack is determined utilizing the instruction. A second plurality of physical registers available to be utilized as a stack are determined whether the second plurality of the quantity. The second plurality of physical registers are then temporarily designated and utilized as a stack.

Abstract: Data is transferred over a bus from one device to another, or between one device and another system resource, such as a central processor. This data is classified into one of several types. "Hard real time" data must be transferred within a specified time limit or "deadline" and it is unacceptable to miss a deadline. "Soft real time" data should be transferred before a deadline and, although some missed deadlines are tolerable, the lower the number of missed deadline the better. "Loss sensitive" data has no deadlines, but any loss of data is unacceptable. "Non-real time" data also has no deadlines, but the lower the time delay in transferring the data the better. The intelligence that controls the transfer of data and schedules access to the bus is distributed throughout the system. Part of this scheduling intelligence is included in the bus arbiter, while the remainder is incorporated in the devices themselves.

Abstract: A computer system is provided which includes a central processing unit (CPU), a main memory, cache memory and a cache controller. The CPU generates a first CPU control signal indicating whether a CPU request is a request for instruction or data and a second CPU control signal indicating whether a request is for retrieving information from memory or for storing information into the memory. The cache controller includes prefetch logic which is responsive to the type of request from the CPU, such as, for example, instruction or data, read or write, for determining the amount of data to be prefetched into the cache memory from the main memory.

Abstract: A processor clock (302) is momentarily synchronized to a subsystem clock (307) during transfers of data between a processor (301) and a subsystem (305). After the completion of the data transfer, synchronization is disabled and the processor clock runs asynchronously at its own internal frequency, which is higher than the subsystem clock frequency. In one embodiment, the processor clock uses a free running ring oscillator (401) that is constructed on the same integrated circuit chip as the processor. Changes in temperature and power supply voltage not only cause changes in the maximum operating speed of the processor, but they also cause corresponding changes in the frequency of the processor clock. Thus, the frequency of the processor clock tracks changes in the maximum operating speed of the processor caused by temperature and power supply variations.

Abstract: A Central Processing Unit is provided having an instruction processor for determining CPU instruction types. An instruction detector is included in the CPU for detecting whether a determined instruction is a non-cacheable repeat operation instruction. The CPU has an execution unit for executing instruction and for outputting a CPU signal indicating whether data associated with an instruction is cacheable.