Abstract: A digital circuit for sensing peaks exceeding a predetermined threshold in nalog signals employs clock and control oscillators arranged such that their frequencies vary in opposite senses in response to changes in the sensed signal. The clock oscillator frequency is counted during sample intervals of durations which vary inversely with the control oscillator frequency. A count increase (or decrease) of predetermined amount from one sample interval to the next, followed by a count decrease (or increase) from another sample interval to the next, results in an output signal. In a preferred embodiment, the clock frequency is counted in an up/down counter which, for each sample interval, is counted up and down for equal numbers of control oscillator cycles. The net count at the end of a sample interval is therefore an indication of the magnitude and polarity of changes in the sensed signal.

Abstract: A tuned circuit resonates to produce a ringing signal. The signal is fed to frequency divider which generates an oscillator output pulse. The pulse is fed back to the tuned circuit for impulse excitation thereof, producing subsequent oscillator output pulses.