Patents by Inventor Thomas Fahrig

Thomas Fahrig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11103780
    Abstract: The present disclosure relates to devices, methods, and computer-readable medium for saving and restoring physical hardware states and virtual machine (VM) states for an application actively being executed on a virtual machine by a user on a computer device. The devices, methods, and computer-readable medium may allow a user to suspend a current state of an application session and save the VM and memory state to persistent storage, and later resume the execution of the saved application session by reading the state back into memory and restoring the VM state.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 31, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Mark James McNulty, Blaine Craig Hauglie, Paul Joseph Wolfteich, Thomas Fahrig, David Neil Cutler
  • Publication number: 20210129024
    Abstract: The present disclosure relates to devices, methods, and computer-readable medium for saving and restoring physical hardware states and virtual machine (VM) states for an application actively being executed on a virtual machine by a user on a computer device. The devices, methods, and computer-readable medium may allow a user to suspend a current state of an application session and save the VM and memory state to persistent storage, and later resume the execution of the saved application session by reading the state back into memory and restoring the VM state.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 6, 2021
    Inventors: Mark James MCNULTY, Blaine Craig HAUGLIE, Paul Joseph WOLFTEICH, Thomas FAHRIG, David Neil CUTLER
  • Patent number: 10691363
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 23, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Fahrig
  • Patent number: 10423451
    Abstract: Computerized methods, computer systems, and computer-readable media for governing how virtual processors are scheduled to particular logical processors are provided. A scheduler is employed to balance a load imposed by virtual machines, each having a plurality of virtual processors, across various logical processors (comprising a physical machine) that are running threads in parallel. The threads are issued by the virtual processors and often cause spin waits that inefficiently consume capacity of the logical processors that are executing the threads. Upon detecting a spin-wait state of the logical processor(s), the scheduler will opportunistically grant time-slice extensions to virtual processors that are running a critical section of code, thus, mitigating performance loss on the front end.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: September 24, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Thomas Fahrig, David Cutler
  • Publication number: 20190227728
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Application
    Filed: January 22, 2019
    Publication date: July 25, 2019
    Inventor: Thomas Fahrig
  • Patent number: 10248459
    Abstract: Embodiments disclosed herein are related to systems, methods, and computer readable medium for allocating one or more system resources for the exclusive use of an application. The embodiments include receiving a request for an exclusive allocation of one or more system resources for a first application, the one or more system resources being useable by the first application and one or more second applications; determining an appropriate amount of the one or more system resources that are to be allocated exclusively to the first application; and partitioning the one or more system resources into a first portion that is allocated for the exclusive use of the first application and a second portion that is not allocated for the exclusive use of the first application, the second portion being available for the use of the one or more second applications.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Gregory John Colombo, Logananth Seetharaman, Graham Wong, Mehmet Iyigun, Steven Michel Pronovost, Thomas Fahrig, Thobias Jones, Michael Charles Crandall, James Andrew Goossen
  • Patent number: 10185514
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Fahrig
  • Publication number: 20180321966
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Patent number: 10067782
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: September 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Publication number: 20180157519
    Abstract: Idle virtual machine partitions in a virtualized computing environment are consolidated onto one or more idle logical processors. A hypervisor monitors the individual utilization of multiple virtual machine partitions in a computing environment and determines which virtual machine partitions are idle. The hypervisor also monitors the individual utilization of multiple logical processors in the computing environment and determines which logical processors are idle. The hypervisor schedules all of the idle virtual machine partitions on one or more of the idle logical processors. This can improve the performance for work-generating partitions and ensure compliance with service level agreements. At the same time, it can provide efficient power management in that is consolidates idle virtual machines onto a smaller subset of logical processors.
    Type: Application
    Filed: October 9, 2017
    Publication date: June 7, 2018
    Inventor: Thomas Fahrig
  • Patent number: 9804874
    Abstract: Idle virtual machine partitions in a virtualized computing environment are consolidated onto one or more idle logical processors. A hypervisor monitors the individual utilization of multiple virtual machine partitions in a computing environment and determines which virtual machine partitions are idle. The hypervisor also monitors the individual utilization of multiple logical processors in the computing environment and determines which logical processors are idle. The hypervisor schedules all of the idle virtual machine partitions on one or more of the idle logical processors. This can improve the performance for work-generating partitions and ensure compliance with service level agreements. At the same time, it can provide efficient power management in that is consolidates idle virtual machines onto a smaller subset of logical processors.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: October 31, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Fahrig
  • Publication number: 20170269867
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Application
    Filed: March 30, 2017
    Publication date: September 21, 2017
    Inventor: Thomas Fahrig
  • Publication number: 20170269968
    Abstract: Embodiments disclosed herein are related to systems, methods, and computer readable medium for allocating one or more system resources for the exclusive use of an application. The embodiments include receiving a request for an exclusive allocation of one or more system resources for a first application, the one or more system resources being useable by the first application and one or more second applications; determining an appropriate amount of the one or more system resources that are to be allocated exclusively to the first application; and partitioning the one or more system resources into a first portion that is allocated for the exclusive use of the first application and a second portion that is not allocated for the exclusive use of the first application, the second portion being available for the use of the one or more second applications.
    Type: Application
    Filed: June 30, 2016
    Publication date: September 21, 2017
    Inventors: Gregory John Colombo, Logananth Seetharaman, Graham Wong, Mehmet lyigun, Steve Michel Pronovost, Thomas Fahrig, Thobias Jones, Michael Charles Crandall, James Andrew Goossen
  • Patent number: 9639292
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: May 2, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Fahrig
  • Publication number: 20160154666
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 2, 2016
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Patent number: 9201673
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: December 1, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, Rene Antonio Vega, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Publication number: 20150324231
    Abstract: Computerized methods, computer systems, and computer-readable media for governing how virtual processors are scheduled to particular logical processors are provided. A scheduler is employed to balance a load imposed by virtual machines, each having a plurality of virtual processors, across various logical processors (comprising a physical machine) that are running threads in parallel. The threads are issued by the virtual processors and often cause spin waits that inefficiently consume capacity of the logical processors that are executing the threads. Upon detecting a spin-wait state of the logical processor(s), the scheduler will opportunistically grant time-slice extensions to virtual processors that are running a critical section of code, thus, mitigating performance loss on the front end.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: THOMAS FAHRIG, DAVID CUTLER
  • Publication number: 20150317179
    Abstract: Computerized methods, computer systems, and computer-readable media for governing how virtual processors are scheduled to particular logical processors are provided. A scheduler is employed to balance a CPU-intensive workload imposed by virtual machines, each having a plurality of virtual processors supported by a root partition, across various logical processors that are running threads and input/output (I/O) operations in parallel. Upon measuring a frequency of the I/O operations performed by a logical processor that is mapped to the root partition, a hardware-interrupt rate is calculated as a function of the frequency. The hardware-interrupt rate is compared against a predetermined threshold rate to determine a level of an I/O-intensive workload being presently carried out by the logical processor. When the hardware-interrupt rate surpasses the predetermined threshold rate, the scheduler refrains from allocating time slices on the logical processor to the virtual machines.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 5, 2015
    Inventor: THOMAS FAHRIG
  • Patent number: 9146785
    Abstract: One embodiment illustrated herein includes a method that may be practiced in a computing environment. The method includes acts for providing direct access to hardware to virtual machines. The method includes determining that a virtual machine should have access to a piece of hardware. The method further includes a virtual machine requesting access to the hardware from the host wherein a host is a special partition that controls the physical hardware of a computing system and manages virtual machines. The method further includes the host configuring the hardware to allow access to the hardware directly by the virtual machine by the host mapping hardware resources into the virtual machine's address space. The method further includes the virtual machine directly accessing the hardware without going through the host once the hardware has been configured by the host.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: September 29, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Fabian Samuel Tillier, Thomas Fahrig
  • Publication number: 20150254110
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Application
    Filed: May 21, 2015
    Publication date: September 10, 2015
    Inventor: Thomas Fahrig