Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.

Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.

Abstract: In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded fields. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the entry. In another form, a system comprises a memory system and a processor coupled to the memory system. The processor is adapted to access the memory module using such a memory controller.

Abstract: In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded fields. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the entry. In another form, a system comprises a memory system and a processor coupled to the memory system. The processor is adapted to access the memory module using such a memory controller.

Abstract: Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).

Abstract: Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).

Abstract: Methods and apparatus are provided for use in testing a memory (230) coupled to a processing node (214). A background scrubber (316) in the processing node (214) is initialized to perform a test of the memory (230). A status of the background scrubber (316) is checked in which the status indicates whether an error occurred during the test. A predetermined action is taken in response to the status indicating that the error occurred during the test.

Abstract: In response to a cold reset in a computer system, a plurality of indications in a nonvolatile memory are initialized to a first state. Each of the plurality of indications is assigned to a respective one of a plurality of tasks to be executed on one or more processors of the computer system. A first task of the plurality of tasks is executed, including changing a first indication of the plurality of indications to a second state, wherein the first indication is assigned to the first task. A computer accessible medium comprising one or more instructions implementing the initialization and one or more instructions comprise the first task is also contemplated, as well as a computer system including a processor and the computer accessible medium.

Abstract: A technique for initializing a memory controller of a plurality of memory modules for optimum system performance is presented. A plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules are determined. A plurality of benchmark calculations using the plurality of optimum sets of operational parameters produces a plurality of benchmark numbers. The memory controller is configured with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers. The benchmark calculations can be based on a variety of conditions, for example, burst length or the minimum time to read a random row of memory. Additionally, the benchmark calculations can be weighted in favor of frequency.

Abstract: An on-screen display system for displaying instructions for guiding a user to utilize various features of a consumer electronics product such as a television receiver or VCR, includes a memory for storing both uncompressed text data and compressed text data, and an associated microprocessor for retrieving the text data, decompressing it if necessary, and presenting it to a display buffer. Text data compression is in part accomplished by a dictionary containing text data representing commonly used text "strings" comprising one or more words which is stored in the memory. Code words related to the location of respective dictionary entries in memory are substituted for respective uncompressed text data.

Abstract: A microprocessor-controlled coin telephone station includes apparatus that enables it to provide dialed telecommunications service and accept payment therefor--which is its primary function. The coin telephone station further includes apparatus for automatically dialing predetermined telephone numbers, automatically answering incoming telephone calls, and apparatus for monitoring conditions associated with its primary function in order to be a participating member of a hierarchal reporting network--which is its secondary function. In order to carry out the secondary function, the coin telephone station stores operating instructions which cause it to operate as either a Master or a Slave station within the hierarchal network.

Abstract: The invention is a UF.sub.6 -recovery process of the kind in which a stream of substantially pure gaseous UF.sub.6 is directed through an externally chilled desublimer to convert the UF.sub.6 directly to an annular solid ring adhering to the interior wall of the desublimer. After accumulation of a desired amount of solid UF.sub.6, the desublimer is heated to liquefy the solid. Subsequently, the liquid is recovered from the desublimer. It has been found that during the heating operation the desublimer is subjected to excessive mechanical stresses. In addition, it has been found that the incorporation of a very small percentage of relatively noncondensable, nonreactive gas (e.g., nitrogen) in the UF.sub.6 input to the desublimer effects significant decreases in the stresses generated during the subsequent melting operation.