Abstract: This disclosure relates to wireless battery charging of electronic devices such as wireless headsets/headphones. In one embodiment, an electronic device is provided comprising a speaker comprising a coil, and the coil is operative both to cause the speaker to produce sound and to receive energy transferred to the coil via inductive coupling. The received energy is used to recharge a rechargeable battery in the electronic device. In other embodiments, the coil used to receive the energy that recharges the battery is received by a coil other than the coil in the speaker.

Abstract: A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.

Abstract: A biasing scheme for compensating for a difference in biasing currents between a first circuit element (10) and second circuit element (32) in a stacked circuit configuration. A current-difference source (38) generates a difference current that is substantially equal to the difference between the biasing currents of the first circuit element (10) and second circuit element (32) in order to compensate for process, temperature and supply variations.

Abstract: A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.

Abstract: A calibration circuit (17) for calibrating a frequency synthesizer (10) having a voltage-controlled oscillator (VCO) (15) with a plurality of switched-capacitor arrays (CA1-CAn). The calibration circuit (17) counts a predetermined number of periods of the reference-clock signal (ref_clk) and divide-clock signal (div_clk) of the frequency synthesizer using a fast clock signal (fastclk). The fast-clock signal (fastclk) has a frequency greater than either the reference-clock signal (ref_clk) or the divide-clock signal (div_clk), enabling significantly faster calibration of the frequency synthesizer (10) than would be possible using the reference-clock signal (ref_clk). The calibration circuit (17) compares the count of the periods of the reference-clock signal (ref_clk) and the divide-clock signal (div_clk) and varies the tank signal of the VCO (VCO_tank_setting) until the count of the periods is substantially equal.

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract: A calibration circuit (17) for calibrating a frequency synthesizer (10) having a voltage-controlled oscillator (VCO) (15) with a plurality of switched-capacitor arrays (CA1-CAn). The calibration circuit (17) counts a predetermined number of periods of the reference-clock signal (ref_clk) and divide-clock signal (div_clk) of the frequency synthesizer using a fast clock signal (fastclk). The fast-clock signal (fastclk) has a frequency greater than either the reference-clock signal (ref_clk) or the divide-clock signal (div_clk), enabling significantly faster calibration of the frequency synthesizer (10) than would be possible using the reference-clock signal (ref_clk). The calibration circuit (17) compares the count of the periods of the reference-clock signal (ref_clk) and the divide-clock signal (div_clk) and varies the tank signal of the VCO (VCO_tank_setting) until the count of the periods is substantially equal.

Abstract: A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract: According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.

Abstract: According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract: A combined charge storage and bandgap reference is disclosed. In one embodiment, a system comprises a bandgap reference circuit; a charge storage circuit, wherein an output of the bandgap reference circuit is provided as an input to the charge storage circuit; and a control circuit in communication with the bandgap reference circuit and the charge storage circuit. The control circuit is operative to control charging of the charge storage circuit by the output of the bandgap reference circuit and control selection of one of the output of the bandgap reference circuit and an output of the charge storage circuit. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

Abstract: In a wireless transmission method, an input data signal corresponding to a serial combination of a first transmit data signal and a second transmit data signal is received. The first and second transmit data signals are phase-modulated with different first and second spreading code signals to produce first and second DSSS transmit signals, which are serially output as a baseband transmit signal that is up-converted to a selected wireless transmission frequency range. The first and second phase-modulated signals are serially output as a baseband transmit signal. In a wireless reception method, an input receive signal is down-converted to a baseband receive signal corresponding to a serial combination of first and second time-interleaved DSSS receive signals in a baseband frequency range. The first and second DSSS receive signals are phase-demodulated with different first and second de-spreading code signals to produce first and second receive data signals.

Abstract: A memory circuit that retains stored data upon power down includes a volatile data storage circuit; and at least one nonvolatile memory coupled within the volatile data storage circuit, wherein the at least one nonvolatile memory includes a high resistive state and a low resistive state. The volatile data storage circuit can include cross-coupled inverters, cross-coupled NAND gates, or another volatile data storage circuit. The nonvolatile memories can include a spin-injection magnetic tunnel junction memory, a magnetic tunnel junction memory, a metal insulator phase change memory, an organic memory, or some other memory with two resistive states.

Abstract: The invention includes a tendon stripper comprising: (a) a frame, including a cautery, that is adapted to separate surrounding tissue along a length of a tendon; (b) a handle mounted to the frame that is adapted to reposition the frame with respect to the tendon; and (c) an actuator in communication with the cautery and operative to activate the cautery, where activation of the cautery is adapted to sever the tendon.

Abstract: A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.