Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: A three-dimensional memory array and method for storing data bits and ECC bits therein is provided. A three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is described. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: An inexpensive method and means for generating high power envelope-modulated radio frequency signals is disclosed. Embodiments provide EER amplification and separate modulation of information encoded as phase angle and as amplitude. An envelope modulated signal generation apparatus comprising a source of carrier signal, a source of a binary data stream, a pulse deletion logic and a current switch is disclosed.

Abstract: A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: The preferred embodiments described herein provide a three-dimensional memory array and method for storing data bits and ECC bits therein. In one preferred embodiment, a three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is provided. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word. Other preferred embodiments are disclosed.