Abstract: A polyphase filter passes a desired frequency and attenuates an image frequency in many communication systems. The invention is an error correction circuit that compensates the polyphase filter for low open loop gain operational amplifiers. When multiple polyphase filters are used in communication circuits on a single integrated circuit (IC), the open loop gain of the operational amplifiers is limited by the IC's ability to dissipate power. The error correction circuit reduces the dependency of the polyphase filter performance on the low open loop gain of its operational amplifiers and hence, on temperature and IC process parameters.

Abstract: An image-rejecting receiver comprises a tunable mixer stage, a time-share I-Q mixer stage, a complex filter, and an image rejector. The time-share I-Q mixer stage includes a switch assembly, inphase and quadrature polarity inverters, and a clock generator. The switch assembly generates pulses and distributes them in alternation to the polarity inverters. Performing distribution prior to polarity inversion preserves the orthogonality of the inphase and quadrature target signal components despite pulse-to-pulse bleeding. Charge accumulated at the distributor switch input is dumped between pulses to further minimize such bleeding. A current-mode field-effect-transistor implementation ensures unity gain across each polarity inverter so that they are gain-matched. Gain matching and preservation of orthogonality optimize the conditions for the complex filter to attenuate and for the image rejector to cancel an image signal.

Abstract: Circuitry and circuitry layout are provided to achieve a high percentage of photoreceiver area to total area and to stabilize the voltage at the base node of a phototransistor. Voltage stabilization is achieved by a servo circuit in which a negative feedback loop from the base node to an emitter node maintains a bias point, so that photocurrent is efficiently delivered to charge transfer circuitry. In the preferred embodiment, the base node is connected to a gate of a first transistor having a drain that is connected to a source of constant current and to a gate of a second transistor that functions as a source follower. The source of the second transistor is connected to the emitter node of a phototransistor. As photocurrent is generated by the reception of light, an integration capacitor is charged.

Abstract: A method and device for tracking relative movement between the device and a region of interest include correlating a reference frame of signals with a subsequently acquired sample frame of signals, with the correlating including generating a correlation output for each of a number of nearest-neighbor shifts of signals of one of the frames. Preferably, the frames are comprised of a two-dimensional array of pixels and the signals are pixel values. The pixels of a frame are operatively associated with photoelements in a two-dimensional array of photoelements, with the pixel values being indicative of light energy received at the photoelements. By correlating the reference frame and the sample frame using the nearest-neighbor approach, it is possible to determine the movement of an imaged feature during the time period between acquisition of the reference frame and acquisition of the sample frame.

Abstract: Circuitry and method for transferring signals from a photoreceiver array to computational circuitry includes parallel transfer amplifiers that receive periodic offset correction and includes DC removal amplifiers. In a first embodiment, each transfer amplifier has a differential circuit that can be switched from a reset mode to a readout mode. In the readout mode, the voltage state at the output is responsive to first and second inputs, with the second input being connected to a source of a reference voltage. In the reset mode, the inputs are both connected to the reference voltage and the output is temporarily connected to a source of a fixed reset voltage. An offset adjustment signal is generated in response to detection of a voltage difference between the reset voltage and the actual voltage state at the output after the output has been disconnected from the source of the reset voltage. A single offset circuit is used to periodically and sequentially refresh the various transfer amplifiers.

Abstract: A time-share mixer circuit and a frequency converter, an I-Q modulator, and an I-Q demodulator. A switching signal drives the time-share mixer circuit to alternate between two output signals. The first output signal represents the output of a mixer having a given signal input and a local oscillator signal with a first phase as its local oscillator input. The second output signal represents the output of the mixer having the same input signal and the local oscillator signal with a second phase that differs from the first phase by 90 degrees as its local oscillator input signal. The frequency converter uses the time-share mixer in combination with a switched output phase shifter that switches in sync with the phase of the local oscillator signal to generate a phase shifted output signal in which the time average of an undesired image signal is substantially reduced compared to time average of the desired signal. The phase shifted output signal is then amplified by a bandpass amplifier.

Abstract: A method of encoding data for transmission over a communication link. A cumulative polarity of previously-transmitted frames is maintained. A frame is prepared for transmission by combining a data word with a plurality of additional bits. The additional bits provide a master transition. A phantom bit is encoded in the additional bits. If the polarity of the frame is the same as the cumulative polarity, the data bits or in some instances all the bits are inverted so as to maintain balance. Control words and fill words are provided and are distinguished from data words by encoding the additional bits. Control words carry additional data or control instructions and are distinguished from fill words by the number of transitions. The phantom bit either conveys additional data or is used for such purposes as error checking.

Abstract: A power amplifier having a gain factor of G for generating an output signal from a low power amplitude and phase modulated input signal. The power amplifier generates first and second constant envelope signals. Each constant envelope signal has the same frequency as said input signal. The first constant envelope signal has the same amplitude as the second constant envelope signal but differs in phase from the first constant envelope signal by an amount depending on the amplitude of the input signal. The output signal is generated by vectorially adding the first and second constant envelope signals. The amplifier has a feedback loop which operates by determining the difference in amplitude between the input signal and a signal having an amplitude 1/G times the amplitude of the output signal. The phase difference between the first and second constant envelope signals is altered so as to reduce the determined difference in amplitude.

Abstract: A circuit for combining first and second signals having the same frequency. The signals have a relative phase shift, 2a(t). The circuit generates a signal that is proportional to the sum or difference of signals. The circuit appears to be a resistive load; however, the circuit can be constructed from purely reactive circuit elements, and hence, does not dissipate energy. In one embodiment, the circuit is constructed from a transformer and two LC circuits in which the capacitance is varied in response to a(t). The circuit may be used to construct a high efficiency RF amplification stage.

Abstract: A bucket brigade analog delay line with voltage limiting feedback includes an input stage for receiving an input signal and a series of delay stages coupled to the input stage for propagating the input signal through the line. Each delay stage contains a storage capacitor for holding either a signal charge or a reference charge, a transfer device for transferring charge from one stage to another at regular clock intervals, and a tap circuit for allowing external sampling of the propagated input signal. Each delay stage also includes a negative feedback amplifier for maintaining the drain terminal of the transfer device at a constant potential during charge transfer, thereby eliminating errors caused by finite output impedance of the transfer device. The negative feedback amplifier also prevents overvoltage conditions which could result in failure of the charge transfer devices.

Abstract: Means and structure for encoding binary data ensures that, on average, the encoded data provides a balanced data stream having an equal number of logical one and logical zero bits. An indicator bit of known value is appended to N data bits, forming a group of N+1 bits. The polarity of this group is determined, i.e. whether the group contains more ones than zeros. The cumulative polarity of all bits sent over the communication link is also maintained. When the polarity of the group is the same as the cumulative polarity, all bits in the group are inverted and the inverted group is transmitted. Otherwise the bits in the group are transmitted in their original form. To decode the transmitted bits, the bit stream is framed to separate each series of N+1 bits. The value of the indicator bit on the receiver side of the communication link indicates whether the group has been inverted. If the group has been inverted, it is reinverted on the receiver side of the link to provide the N data bits in their original form.

Abstract: A sample-and-hold circuit distinguished by its lack of a storage capacitor. The circuit includes a delay line and a signal following circuit coupled to the delay line which is synchronized with the delay line's propagation rate. In several embodiments of the invention a multi-tap delay line is used, and the signal following circuits variously include an electronic switch or linear interpolation circuits. In several other embodiments of this invention a gate of a FET is used as the delay line, and the signal following circuits include the drain and source of the FET. By substituting a delay line and signal following means for a storage capacitor, extremely fast sample-and-hold circuits may be obtained.

Abstract: A digital signal regenerator comprises a quantizer, a sampler, a timing extractor and a frequency and phase locked loop. The included frequency locked loop employs a frequency difference detector and a frequency generator which it shares with the included phase locked loop. The frequency difference detector includes flip-flops for generating square wave frequency difference signals, obviating the need for the multipliers, comprators and low pass filters used in prior devices. In addition, the frequency difference detector includes pulse-width modulator which is controlled by a pulse-width regulator. The regulator provides for a constant loop gain for the frequency locked loop over different reference frequencies output by the frequency generator.

Abstract: A low distortion differential sampler circuit implemented in GaAs is provided. The sampler circuit constitutes an on/off switching circuit rather than a sample and hold circuit. Elimination of the holding capacitor results in shorter switching times and reduced error. The sampler implements a differential, balanced architecture which compensates for clock signal feed through. The sampler circuit includes a three-stage, AC coupled GaAs pre-amplifier which provides a complementary clock signal to drive the sampler and sets the DC levels.

Abstract: A binary scaled current source in which a set of binary switches M.sub.1, . . . , M.sub.n controllably switch a current I to a selected one of a set of n outputs. Each switch M.sub.k is controlled by an associated control signal B.sub.k having a duty cycle of 2.sup.k-n-1. At any given time one and only one of the control signals is high so that the current I is diverted to the kth output a fraction 2.sup.k-n-1 of the time. In two particular schemes referred to as the weighted pulse width (WPW) and the weighted repetition rate (WRR) schemes, all of the control signals are periodic with a group pattern repetition period T. In the WPW scheme, B.sub.k has in each period T a single pulse of duration 2.sup.k-n-1 *T. In the WRR scheme, B.sub.k has in each period T2.sup.k-1 pulses each of duration 2.sup.-n *T. The output of each binary switch is typically passed through a low pass filter which conducts substantially only the dc component of the output current from the binary switch to which it is connected.

Abstract: A pulsed current source in which the dc component of the pulsed current is independent of variations in the duty cycle of the current pulses. A dc current source supplies a current I through a switch that alternately switches the current between a first output and a second output to produce at the first output the pulsed current I.sub.p. The dc component of the current at the second output is added to the current I, thereby making the dc component of the pulsed current insensitive to the duty cycle. In systems in which additional processing produces from I.sub.p a set of currents, the dc component of the sum of a first subset of these currents is made to equal I by adding to the input of the switch the dc component of the sum of those currents in the complement of the first subset.

Abstract: A bit cell is presented which can provide a small weighted current without loss of switching speed. The bit cell contains a switch which is responsive to an applied control signal to direct the weighted current to an output or to divert it away from the output. Supplementary currents are supplied to the switch to provide sufficient current to the switch to charge and discharge parasitic capacitances of the switch within the switching time of the control voltage. The supplementary currents maximize switching speed at a given power dissipation and produce a constant offset current at the switch output. A D/A converter is presented which utilizes a plurality of such bit cells to maximize the speed of D/A conversion. The offset currents are eliminated from the converter output so that the output current is proportional to the digital input.

Abstract: A system is provided in which an analog storage device stores, delays, and/or changes the time scale of an input analog waveform. The system provides an output which is corrected for the gain and offset of the analog storage device by exercising the system using known analog inputs and combining the output so obtained with the uncorrected output of the input analog waveform. In a preferred embodiment, the output is also corrected for non-linear and dispersive distortion of the storage device by exercising the system using an input analog signal derived from the earlier output of the system (corrected for gain and offset) and suitably combining the new output so generated with the earlier output.

Abstract: A transient storage instrument of the charge coupled device (CCD) type captures fast analog transient signals and reproduces them at a slower rate. A number of stages of a "sampling" CCD sample and store charges representing time sampled voltages on the transient signal. The stored charges are then transferred in parallel into a "storage" CCD shift register to be stored and serially outputted as a time sequence of output voltage levels representative of the input signal at each of the sample times.

Abstract: A charge-splitting device and method include a plurality of charge cells coupled to receive a charge in response to being simultaneously clocked into a charge receiving state by an applied clock signal. The received charge is split into predetermined charge portions among the plurality of charge cells in proportions dependent upon the total number of cells, their relative capacitance and the magnitude and timing of the applied clock signal. The charge portions are again split and selectively summed to obtain highly accurate charge splitting ratios.