Abstract: An encoder obtains an uncompressed video bitstream that includes syntax elements that are to be coded using multi-symbol alphabets such that at least one syntax element of the syntax elements that are to be coded determines a magnitude token level that is at least partially represented by a head part. For each of the at least one syntax element, the encoder encodes the head part using multi-symbol alphabets to include a magnitude token level and end-of-block (EOB) information. The encoder transmits to a decoder an encoded bitstream that includes syntax elements coded with the multi-symbol alphabets.

Abstract: In one embodiment, one or more portions of video content that were encoded by a video encoder are identified. The one or more portions of video content are to be analyzed for improving encoding performance of the video encoder. The one or more portions of the video content are stored. During an idle time period of the video encoder, the one or more portions of video content are analyzed in combination with a test set stored by the video encoder in order to modify one or more functions of an encoding process used by the video encoder. Based on the analysis, one or more modifications to the encoding process are determined that result in improved performance of the video encoder.

Abstract: A method comprises: obtaining, at an apparatus, first voice data from a first user device associated with a first speaker participant in a communication session; detecting voice data loss or degradation in the first voice data; determining whether prediction probability of correctly compensating for the voice data loss or degradation is greater than a predetermined probability threshold; if the prediction probability is greater than the predetermined probability threshold, first compensating for the voice data loss or degradation using historical voice data received by the apparatus prior to receiving of the first voice data, the first compensating producing first compensated voice data; if the prediction probability is not greater than the predetermined probability threshold, second compensating for the voice data loss or degradation by inserting noise to the first voice data to produce second compensated voice data; and outputting the first compensated voice data or the second compensated voice data.

Abstract: In one embodiment, one or more portions of video content that were encoded by a video encoder are identified. The one or more portions of video content are to be analyzed for improving encoding performance of the video encoder. The one or more portions of the video content are stored. During an idle time period of the video encoder, the one or more portions of video content are analyzed in combination with a test set stored by the video encoder in order to modify one or more functions of an encoding process used by the video encoder. Based on the analysis, one or more modifications to the encoding process are determined that result in improved performance of the video encoder.

Abstract: A method comprises: obtaining, at an apparatus, first voice data from a first user device associated with a first speaker participant in a communication session; detecting voice data loss or degradation in the first voice data; determining whether prediction probability of correctly compensating for the voice data loss or degradation is greater than a predetermined probability threshold; if the prediction probability is greater than the predetermined probability threshold, first compensating for the voice data loss or degradation using historical voice data received by the apparatus prior to receiving of the first voice data, the first compensating producing first compensated voice data; if the prediction probability is not greater than the predetermined probability threshold, second compensating for the voice data loss or degradation by inserting noise to the first voice data to produce second compensated voice data; and outputting the first compensated voice data or the second compensated voice data.

Abstract: Techniques are presented herein for coding non-binary syntax elements in video coding, including coefficients, by using a symbol-adaptive multi-symbol arithmetic code. These techniques achieve coding gain, reduce or eliminate the deficit of error-resilient versus non-error resilient coding, eliminate the compressed header and reduce the symbol throughput in entropy coding.

Abstract: An integrated circuit system (120) includes a memory array (122) storing a configuration data set to configure an integrated circuit. The integrated circuit (121) includes a configuration memory (128) and a configuration controller state machine (126). The configuration controller state machine operates so as to read a read-check signature at a read-check address of the memory array (122) and to compare the read-check signature with a standard signature stored in the integrated circuit (121). If the read-check signature passes the comparison, the configuration controller state machine (126) loads the configuration data set from the memory array to the configuration memory (128) of the integrated circuit.

Abstract: Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.

Abstract: Described are programmable logic devices with configuration memory cells that function both as RAM and ROM. A PLD incorporating these memory cells to store configuration data can be mask-programmed with a customer design, rendering the PLD an application-specific integrated circuit (ASIC). The mask programming can be selectively disabled, in which case each configuration memory cell behaves as a static, random-access memory (SRAM) bit. In this mode, a PLD employing these dual-mode memory cells behaves as a reprogrammable PLD, and can therefore be tested using generic test procedures developed for the PLD. The dual-mode memory cells thus eliminate the burdensome task of developing application-specific test procedures for designs ported from a PLD. As an added benefit, in the ROM mode these memory cells are not susceptible to radiation-induced upsets, so for example, PLDs incorporating these memory cells are better suited for aerospace applications than conventional SRAM-based PLDs.

Abstract: Described are area-efficient non-volatile memory systems. Non-volatile memory cells in these systems include only one transistor, two fewer than conventional non-volatile memory cells, and reduced interconnect. The simplicity of the memory cells reduces memory-system area, improves manufacturing yield, and consequently reduces cost. New program, erase, and read methodologies have been developed for use with the simplified memory cells.

Abstract: A non-volatile product term cell is provided having a first floating gate located over a first p-channel transistor and a first n-channel transistor, and a second floating gate located over a second p-channel transistor and a second n-channel transistor. A control gate is located over the first and second floating gates. A first tunnel oxide capacitor is coupled to the first floating gate and a second tunnel oxide capacitor is coupled to the second floating gate. A first transistor pair is coupled between the first p-channel transistor and the second n-channel transistor, and a second transistor pair is coupled between the second p-channel transistor and the first n-channel transistor. The first and second floating gates are programmed and/or erased. Complementary input signals are applied to the first and second transistor pairs. An output signal is provided in response to the programmed/erased states of the first and second floating gates.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: A level shifter for low voltage operation includes two level shifting stages. The first stage shifts the input voltage level to an intermediate voltage level, and the second stage shifts the intermediate voltage level to an output voltage level. This two-stage arrangement allows the level shifter to function for very low input voltages, and enables functionality across a wide range of output voltages. The first stage is designed to be compatible with very low input voltages and the intermediate voltage level is chosen to be within the safe operating limits of the first stage. The intermediate voltage level is also high enough to drive the high voltage devices of the second stage. This level shifter can be used where multiple output voltage levels are required depending on the particular application or operating mode.

Abstract: Described are circuits and methods for automatically measuring the program threshold voltage VTP and the erase threshold voltage VTE of EEPROM cells. The measured threshold voltages are employed to measure tunnel-oxide thickness and to determine optimal program and erase voltage levels for EEPROM circuits. One embodiment automatically sets the program and erase voltages based on the measured threshold voltages.

Abstract: A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data while the CPLD is operating in a first configuration. This relatively time-consuming operation has no effect on CPLD operation since only the SRAM array controls the configuration of the CPLD. At a desired point in time, the new configuration data from the EEPROM array can be loaded into the SRAM array to reconfigure the CPLD. Because this loading of configuration data into the SRAM array takes only microseconds to perform, normal system operation effectively proceeds without interruption. A CPLD can include multiple EEPROM arrays, each storing a different set of configuration data, thereby allowing the CPLD to rapidly switch between various configurations by loading the configuration data from different EEPROM arrays into the SRAM array.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: A ramp-up circuit on an integrated circuit receives a relatively high program (erase) voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program (erase) voltage to prevent damage to the memory cell. The ramp-up circuit includes a pass gate and associated control circuitry that provides a controlled, ramped-up version of the program (erase) voltage to the memory cell without raising internal circuit nodes above the program (erase) voltage.

Abstract: A programmable reference voltage controls a high-voltage source via a programmable voltage divider. The programmable voltage divider scales a fixed reference voltage to a scaled reference value that is used to control the generation of a high voltage source. A comparator provides a feedback signal that is based on a difference between the scaled reference voltage and a scaled output voltage. This feedback signal controls the voltage-controlled output voltage source, so as to track the scaled reference value. In a preferred embodiment, the scale factor associated with the output voltage remains constant, whereas the scale factor associated with the reference voltage is programmable. In alternative embodiments of this invention, the reference scaling factor defaults to a mid-range value, and a bias offset is provided to easily select an output voltage value for either programming or erasing the contents of a programmable memory device.

Abstract: A programmable reference voltage controls a high-voltage source via a programmable voltage divider. The programmable voltage divider scales a fixed reference voltage to a scaled reference value that is used to control the generation of a high voltage source. A comparator provides a feedback signal that is based on a difference between the scaled reference voltage and a scaled output voltage. This feedback signal controls the voltage-controlled output voltage source, so as to track the scaled reference value. In a preferred embodiment, the scale factor associated with the output voltage remains constant, whereas the scale factor associated with the reference voltage is programmable. In alternative embodiments of this invention, the reference scaling factor defaults to a mid-range value, and a bias offset is provided to easily select an output voltage value for either programming or erasing the contents of a programmable memory device.

Abstract: A precharge circuit is provided that produces a reference voltage that can be used for the precharge process, without a direct current flow from the supply voltage. In a preferred embodiment of this invention, the precharge circuit precharges one bus to the supply voltage, and the other bus to ground potential, then, while each bus is capacitively charged to each of the supply and ground potentials, the buses are connected together. Assuming substantially equal capacitance on each bus, the resultant voltage on each bus will be half the supply voltage. A charge transfer effects the precharging of the buses to the supply and ground potential; the only current drawn from the power source is the transient current associated with a switch of capacitive loads.