Abstract: A computer implemented method for performing testing of a computer model of an integrated circuit design is disclosed. The method includes initially generating a first AVF test file for a first integrated circuit design having slow characteristics. Then, the method proceeds to generate a second AVF test file for a second integrated circuit design having fast characteristics. Once the two AVF test files are generated, the method proceeds to comparing test file parameters from the first AVF test file and the second AVF test file. Based on the comparisons, the method proceeds to generate a modified AVF test file that replaces miscompares (i.e., cycle slips) between output signals of the first and second AVF test files with don't care values. The method also includes options for performing pin margining. The pin margining operations are configured to make modifications to the AVF test files in order to compensate for expected physical test station adjustments.

Abstract: Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models.