Patents by Inventor Thomas Kilger

Thomas Kilger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9275878
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20160035677
    Abstract: A method for forming a package arrangement is provided, which may include: arranging at least one chip over a carrier; at least partially encapsulating the at least one chip with encapsulation material, wherein the encapsulation material is formed such that at least a portion of the carrier is uncovered by the encapsulation material; forming an electrically conductive structure over the encapsulation material and on the portion of the carrier uncovered by the encapsulation material; removing the carrier; and then forming a redistribution structure over the chip and the electrically conductive structure, wherein the redistribution structure electrically couples the electrically conductive structure and the chip.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 4, 2016
    Inventors: Ulrich Wachter, Thomas Kilger
  • Publication number: 20160005728
    Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Inventor: Thomas Kilger
  • Patent number: 9147585
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: September 29, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Patent number: 9136213
    Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: September 15, 2015
    Assignee: Infineon Technologies AG
    Inventor: Thomas Kilger
  • Patent number: 9099454
    Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: August 4, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Veronika Huber, Thomas Kilger, Ralf Otremba, Bernd Stadler, Dominic Maier, Klaus Schiess, Andreas Schlögl, Uwe Wahl
  • Patent number: 9041505
    Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Urs Elrod, Christiane Brunner, Thomas Kilger
  • Publication number: 20150091171
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20150064846
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Publication number: 20150041967
    Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Ulrich Wachter, Veronika Huber, Thomas Kilger, Ralf Otremba, Bernd Stadler, Dominic Maier, Klaus Schiess, Andreas Schlögl, Uwe Wahl
  • Publication number: 20150028435
    Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.
    Type: Application
    Filed: August 7, 2014
    Publication date: January 29, 2015
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Patent number: 8890284
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Patent number: 8828807
    Abstract: A method of packaging integrated circuits includes providing a molded substrate including a first plurality of functional semiconductor dies and a plurality of placeholders laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the placeholders. The exposed placeholders are removed to form cavities in the molded substrate. A second plurality of functional semiconductor dies is inserted in the cavities formed in the molded substrate. Electrical connections are formed to the first plurality and second plurality of functional semiconductor dies at a side of the dies uncovered by the molding compound.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20140239438
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Publication number: 20140070913
    Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 13, 2014
    Applicant: Infineon Technologies AG
    Inventors: Gottfried Beer, Urs Elrod, Christiane Brunner, Thomas Kilger
  • Publication number: 20140036464
    Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Thomas Kilger
  • Patent number: 8552828
    Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 8, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Urs Elrod, Christiane Brunner, Thomas Kilger
  • Patent number: 7847387
    Abstract: An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 7, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Horst Theuss
  • Publication number: 20090127638
    Abstract: An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kilger, Horst Theuss
  • Patent number: 7354797
    Abstract: An electronic device has external contact elements projecting from at least one external contact side of a plastic housing. The external contact elements have an internal section and an external section. The external section has an external contact region tapering away from the external contact side. An external contact element of this type improves the possibilities of a soldering connection to circuit carriers of superordinate circuits.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Stefan Paulus