Patents by Inventor Thomas N. Hastings

Thomas N. Hastings has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8064087
    Abstract: A method to modify the availability of one or more attributes within a print network. One or more devices are interrogated to determine associated attributes. A first set of attribute combinations that cause device failure is determined and placed in an unsupported bank for each device. A second set of attribute combinations that do not cause device failure are determined and placed in a supported bank for each device. Access to the first set of attribute combinations is disabled and access to the second set of attribute combinations is enabled.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: November 22, 2011
    Assignee: Xerox Corporation
    Inventors: Christine M. Miyachi, John Y. Zhang, Gerald A. Wedekind, Thomas N. Hasting
  • Patent number: 7944572
    Abstract: A system facilitates communication between a control component and a plurality of processing components. One or more processing components performs one or more tasks, each processing component has at least one attribute associated therewith. One or more attribute banks are associated with each of the one or more processing components, wherein each attribute bank stores the at least one attribute. A control component initiates the one or more tasks for each processing component. A universal driver facilitates communication between the one or more processing components and the control component. The driver includes an interrogation component that queries the one or more processing components to receive the at least one attribute associated with each processing component. A constraint evaluator determines combinations of attributes that are supported and unsupported for each of the one or more processing components.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: May 17, 2011
    Assignee: Xerox Corporation
    Inventors: Christine M. Miyachi, John Y. Zhang, Gerald A. Wedekind, Thomas N. Hastings
  • Publication number: 20100321733
    Abstract: A system facilitates communication between a control component and a plurality of processing components. One or more processing components performs one or more tasks, each processing component has at least one attribute associated therewith. One or more attribute banks are associated with each of the one or more processing components, wherein each attribute bank stores the at least one attribute. A control component initiates the one or more tasks for each processing component. A universal driver facilitates communication between the one or more processing components and the control component. The driver includes an interrogation component that queries the one or more processing components to receive the at least one attribute associated with each processing component. A constraint evaluator determines combinations of attributes that are supported and unsupported for each of the one or more processing components.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Applicant: Xerox Corporation
    Inventors: Christine M. Miyachi, John Y. Zhang, Gerald A. Wedekind, Thomas N. Hastings
  • Publication number: 20080180722
    Abstract: A system facilitates communication between a control component and a plurality of processing components. One or more processing components performs one or more tasks, each processing component has at least one attribute associated therewith. One or more attribute banks are associated with each of the one or more processing components, wherein each attribute bank stores the at least one attribute. A control component initiates the one or more tasks for each processing component. A universal driver facilitates communication between the one or more processing components and the control component. The driver includes an interrogation component that queries the one or more processing components to receive the at least one attribute associated with each processing component. A constraint evaluator that determines combinations of attributes that are supported and unsupported for each of the one or more processing components.
    Type: Application
    Filed: January 26, 2007
    Publication date: July 31, 2008
    Inventors: Christine M. Miyachi, John Y. Zhang, Gerald A. Wedekind, Thomas N. Hastings
  • Patent number: 4338663
    Abstract: A digital data processing system with a central processor for responding to diverse instructions including instructions for calling subroutines. When the central processor executes a calling instruction, the central processor saves information corresponding to the operating environment for the calling routine and then utilizes corresponding information in the subroutine to establish the operating environment for the subroutine. A common return instruction at the completion of each subroutine causes the central processor to retrieve the saved operating information thereby to reestablish the operating environment for the calling routine.
    Type: Grant
    Filed: September 18, 1980
    Date of Patent: July 6, 1982
    Assignee: Digital Equipment Corporation
    Inventors: William D. Strecker, Thomas N. Hastings, Richard F. Lary, David P. Rodgers, Steven H. Rothman
  • Patent number: 4241399
    Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: December 23, 1980
    Assignee: Digital Equipment Corporation
    Inventors: William D. Strecker, Thomas N. Hastings, Richard F. Lary, David P. Rodgers, Steven H. Rothman
  • Patent number: 4241397
    Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: December 23, 1980
    Assignee: Digital Equipment Corporation
    Inventors: William D. Strecker, Thomas N. Hastings, Richard F. Lary, David P. Rodgers, Steven H. Rothman
  • Patent number: 4236206
    Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.
    Type: Grant
    Filed: October 25, 1978
    Date of Patent: November 25, 1980
    Assignee: Digital Equipment Corporation
    Inventors: William D. Strecker, Thomas N. Hastings, Richard F. Lary, David P. Rodgers, Steven H. Rothman
  • Patent number: 3999163
    Abstract: A secondary storage facility including magnetic tape, disk or drum units or other sequential access storage units. Each storage unit or drive connects to a controller by means of a device bus with asynchronous and synchronous paths. Status and controller information is coupled between the controller and a selected drive unit asynchronously over the asynchronous bus. Actual data transfers occur between the controller and a drive over the synchronous bus and between other units in the system and the controller using direct memory access or equivalent data transfers.
    Type: Grant
    Filed: January 10, 1974
    Date of Patent: December 21, 1976
    Assignee: Digital Equipment Corporation
    Inventors: John V. Levy, Steven R. Jenkins, Victor Ku, Peter McLean, Thomas N. Hastings