Patents by Inventor Thomas Ordas

Thomas Ordas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10878132
    Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 29, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Patent number: 10769513
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Patent number: 10734329
    Abstract: In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Publication number: 20190354728
    Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Thomas ORDAS, Yanis LINGE, Jimmy FORT
  • Patent number: 10473709
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Publication number: 20190268137
    Abstract: The disclosure concerns implementing, by a cryptographic circuit, a set of substitution operations of a cryptographic process involving a plurality of substitution tables. For each set of substitution operations of the cryptographic process, a series of sets of substitution operations are performed. One set of the series is a real set of substitution operations corresponding to the set of substitution operations of the cryptographic process. One or more other sets are dummy sets of substitution operations, each dummy set being based on a different permutation of said substitution tables.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Inventors: Yanis LINGE, Thomas ORDAS, Pierre-Yvan LIARDET
  • Publication number: 20190268136
    Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Inventors: Thomas ORDAS, Yanis LINGE
  • Publication number: 20190268134
    Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm based on a scrambled substitution table. For each set of one or more substitution operations of the cryptographic algorithm, the circuit performs a series of sets of one or more substitution operations of which: one is a real set of one or more substitution operations defined by the cryptographic algorithm, the real set of one or more substitution operations being based on input data modified by a real scrambling key; and one or more others are dummy sets of one or more substitution operations, each dummy set of one or more dummy substitution operations being based on input data modified by a different false scrambling key.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Inventors: Daniele FRONTE, Yanis LINGE, Thomas ORDAS
  • Patent number: 10361164
    Abstract: An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 23, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Thomas Ordas, Alexandre Sarafianos, Fabrice Marinet, Stephane Chesnais
  • Publication number: 20190147771
    Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 16, 2019
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge
  • Publication number: 20190122090
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Publication number: 20190079133
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Thomas ORDAS
  • Patent number: 10198683
    Abstract: An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 5, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Publication number: 20180373899
    Abstract: A circuit module of an integrated circuit is located in a first zone of a semiconductor substrate. A decoy cell includes an antenna above a second zone of the semiconductor substrate. The second zone is different from the first zone. A generation circuit operates to generate a decoy electrical signal on the basis of a first electrical signal that is characteristic of an operation of the circuit module and of at least one pseudo-random parameter. The decoy electrical signal is circulated through the antenna so as to generate a decoy electromagnetic radiation.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Thomas ORDAS, Alexandre SARAFIANOS
  • Patent number: 10148421
    Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 4, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Thomas Ordas, Alexandre Sarafianos, Stephane Chesnais, Fabrice Marinet
  • Publication number: 20180341788
    Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.
    Type: Application
    Filed: March 14, 2018
    Publication date: November 29, 2018
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Publication number: 20180253633
    Abstract: In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
    Type: Application
    Filed: November 2, 2017
    Publication date: September 6, 2018
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Publication number: 20180189624
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Application
    Filed: October 31, 2017
    Publication date: July 5, 2018
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Publication number: 20180005964
    Abstract: An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region.
    Type: Application
    Filed: March 1, 2017
    Publication date: January 4, 2018
    Inventors: Thomas Ordas, Alexandre Sarafianos, Fabrice Marinet, Stephane Chesnais
  • Publication number: 20170250795
    Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.
    Type: Application
    Filed: July 28, 2016
    Publication date: August 31, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Thomas Ordas, Alexandre Sarafianos, Stephane Chesnais, Fabrice Marinet