Patents by Inventor Thomas Rabenalt

Thomas Rabenalt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903859
    Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
  • Publication number: 20200301614
    Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 24, 2020
    Inventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
  • Publication number: 20200293402
    Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Jan OTTERSTEDT, Jayachandran BHASKARAN, Michael GOESSEL, Thomas RABENALT
  • Publication number: 20190312601
    Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 10, 2019
    Inventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
  • Patent number: 10200065
    Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt, Stephane Lacouture
  • Patent number: 10157095
    Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: December 18, 2018
    Assignee: Infineon Technologies AG
    Inventors: Jan Otterstedt, Michael Gössel, Thomas Rabenalt, Thomas Kern
  • Patent number: 10067826
    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Publication number: 20170308431
    Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.
    Type: Application
    Filed: April 19, 2017
    Publication date: October 26, 2017
    Inventors: Jan Otterstedt, Michael Gössel, Thomas Rabenalt, Thomas Kern
  • Publication number: 20160306696
    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Patent number: 9450613
    Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Michael Goessel, Klaus Oberlaender, Christian Badack
  • Patent number: 9417957
    Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Rex Kho, Thomas Rabenalt
  • Patent number: 9405618
    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Publication number: 20150347227
    Abstract: A method for accessing a non-volatile memory is presented. The method comprises reading a first memory region of the non-volatile memory and ascertaining whether the first memory region contains a predetermined data pattern. The predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method also comprises evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region. A corresponding memory controller is also disclosed.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Patent number: 9203437
    Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v?=v?1, . . . , v?n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n? column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 1, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Christian Badack, Michael Goessel
  • Patent number: 9118351
    Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: August 25, 2015
    Assignee: Infineon Technologies AG
    Inventors: Antonio Vilela, Rainer Faller, Michael Goessel, Simon Brewerton, Glenn Ashley Farrall, Neil Stuart Hastie, Boyko Traykov, David Addison, Klaus Oberlaender, Thomas Rabenalt
  • Publication number: 20150100827
    Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Inventors: Rex Kho, Thomas Rabenalt
  • Patent number: 8966355
    Abstract: An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt
  • Publication number: 20150007001
    Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 1, 2015
    Inventors: Thomas Kern, Ulrich Backhausen, Thomas Rabenalt, Michael Goessel, Klaus Oberlaender, Christian Badack
  • Patent number: 8898535
    Abstract: An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Ulrich Backhausen, Michael Goessel, Thomas Rabenalt
  • Patent number: 8898529
    Abstract: A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m<N) and wherein the masked test data are compacted by a compactor with N data inputs and n data outputs and m<N applies is provided.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: November 25, 2014
    Assignee: Universität Potsdam
    Inventors: Michael Goessel, Michael Richter, Thomas Rabenalt