Patents by Inventor Thomas S. Maddern

Thomas S. Maddern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7545797
    Abstract: In a partially interconnected topological network having at least six topological nodes, a topological node being a single physical node or a group of interconnected physical nodes or part of a physical node or a group of interconnected physical nodes and parts of physical nodes, each topological node having at least three point-to-point topological links connecting it to some, but not all, of the plurality of topological nodes, there is at least one choice of routing between any two topological nodes, where the choice of routing is either two point-to-point topological links connected in series at another of the topological nodes or a direct point-to-point topological link between the two topological nodes.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: June 9, 2009
    Assignee: Ericsson AB
    Inventors: Bruce Jensen, Peter Bladon, Thomas S Maddern, Geoffrey Chopping
  • Publication number: 20030198213
    Abstract: In a partially interconnected topological network having at least six Topological Nodes, a Topological Node being a single Physical Node or a group of interconnected Physical Nodes or part of a Physical Node or a group of interconnected Physical Nodes and parts of Physical Nodes, each Topological Node having at least three point-to-point Topological Links connecting it to some but not all of the plurality of Topological Nodes and there being at least one Choice of routing between any two Topological Nodes, where a Choice of routing is either two point-to-point Topological Links connected in series at another of the Topological Nodes or a direct point-to-point Topological Link between the two Topological Nodes.
    Type: Application
    Filed: April 8, 2003
    Publication date: October 23, 2003
    Inventors: Bruce Jensen, Peter Bladon, Thomas S Maddern, Geoffrey Chopping
  • Patent number: 5610928
    Abstract: In a telecommunications duplicated synchronous switch where switching in bit synchronism is carried out and fault detection is by discrepancy checking between the duplicate switch planes, determination of the faulty plane is provided by the data being carried in switched bytes grouped into data frames, each frame carrying check data in respect of data from an earlier frame. Corruption of data in a frame is thus indicated by information in a later frame.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: March 11, 1997
    Assignee: GPT Limited
    Inventors: Thomas S. Maddern, James K. Saunders
  • Patent number: 5579311
    Abstract: In a telecommunications system in which narrowband or guiding services already exist, different service rates, either fixed or variable may be required. A further service switch is connected in parallel with the existing narrowband or guiding switch, the further service switch being similarly controlled in response to the guiding signalling.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: November 26, 1996
    Assignee: GPT Limited
    Inventors: Geoffrey Chopping, Thomas S. Maddern, Paul A. Smith
  • Patent number: 5544168
    Abstract: An ATM telecommunications switch includes a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port. A single data stream is divided between a plurality of input ports and the data is concatenated from a plurality of output ports to reconstitute the data stream. A first rotator connects each input port cyclically to each timelslot of the central switching unit and a second rotator connects each timeslot of the central switching unit cyclically to each output port.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: August 6, 1996
    Assignee: GPT Limited
    Inventors: Mark T. Jeffrey, Thomas S. Maddern, Richard J. Proctor
  • Patent number: 5459724
    Abstract: An ATM telecommunications switch includes a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port. Data from a single timeslot on the central switching unit is connected to a plurality of output ports in a point to multipoint operation. A multipoint memory stores information regarding the data addresses and a forward transfer store provides additional storage for multipoint cells.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: October 17, 1995
    Assignee: GPT Limited
    Inventors: Mark T. Jeffrey, Thomas S. Maddern, Richard J. Proctor
  • Patent number: 5303232
    Abstract: The invention concerns an Asynchronous Transfer Mode Switch having a plurality of input stages (IS1 . . . 1SN) each for receiving a digital data transmission stream (DS1 . . . 256) consisting of a series of cells and wherein each input stage of the switch includes a circuit (52) for determining the destination of the cells of that data stream, and a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages.
    Type: Grant
    Filed: April 3, 1991
    Date of Patent: April 12, 1994
    Assignee: GPT Limited
    Inventors: Richard J. Proctor, Thomas S. Maddern, Mark T. Jeffrey, Alexander Philip
  • Patent number: 5271004
    Abstract: An asynchronous transfer mode switching arrangement includes a serial to parallel converter arranged to receive input packets of data, which include routing information, in serial form and convert the packets of data to parallel form. A first random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the first random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output. The first random access memory and the output queues are controlled by a memory management arrangement to which is connected a broadcast channel routine second random access memory.
    Type: Grant
    Filed: August 27, 1991
    Date of Patent: December 14, 1993
    Assignee: GPT Limited
    Inventors: Richard J. Proctor, Thomas S. Maddern
  • Patent number: 5123021
    Abstract: A telecommunication apparatus in which data messages are routed across a switch, each message comprising a message portion and an incoming message identity portion, includes circuitry for generating from the incoming message identity portion an outgoing message identity portion, a switching circuit for utilizing the incoming and outgoing message identity portions to route the message to an output port, circuitry for utilizing the outgoing message identity portion to generate a further message identity portion, and comparator circuitry for comparing the incoming and further message identity portions to detect faults.
    Type: Grant
    Filed: August 16, 1990
    Date of Patent: June 16, 1992
    Assignee: GEC Plessey Telecommunications Limited
    Inventors: Richard J. Proctor, Geoffrey Chopping, Thomas S. Maddern
  • Patent number: 5109378
    Abstract: An asynchronous time division (ATD) switch for carrying out packet switching. In one embodiment a switch has 256 ports running at 155 M bits and is capable of switching incoming data cells at each of the input ports to any one of 256 output ports. At each input port a switch sequentially distributes the received data cells over 16 outputs each of which is connected to a different DMR circuit. There are 256 DMR circuits each having 16 inputs and 16 outputs. A DMR circuit is a fixed space switching device which has N inputs, N time intervals and N outputs and operates cyclically so that each input goes to each output for 1/Nth of the time. The inner stage of the ATD switch comprises 256 central switches each having 16 inputs and 16 outputs. Each central stage switch has its 16 inputs connected to 16 different DMR circuits. The fourth stage of the switch consists of another array of 256 output DMR circuits with each central switch being connected to 16 different output DMR circuits.
    Type: Grant
    Filed: October 12, 1989
    Date of Patent: April 28, 1992
    Assignee: Gec Plessey Telecommunications Limited
    Inventors: Richard J. Proctor, Thomas S. Maddern, Alexander S. Philip
  • Patent number: 5042038
    Abstract: A data pathchecking system for resolving data transfer errors in a plane of directly connected switching elements, the system checking the plane of directly connected switching elements by designating one switching element with an associated control element as a master and other switching elements and associated control elements as slaves. The master switch element instructs other switch elements discretely to check their respective switching element for data transfer errors and checks its own switching element for data transfer errors. Furthermore, the master switch is arranged to validate connections between switching elements.
    Type: Grant
    Filed: April 17, 1989
    Date of Patent: August 20, 1991
    Assignee: Plessey Overseas Limited
    Inventors: Richard J. Proctor, Thomas S. Maddern
  • Patent number: 4912700
    Abstract: In order to permit multislot connections to be simply made across a telecommunications digital switch, so that all the slots of the multislot connection experience the same whole frame time delay, the switch is constructed as input and output switch stages each comprising arrays of digital switching modules (DSM) and a central switching area comprising two arrays of Demultiplexing/Mixing/Remultiplexing devices (DMR) interconnected by an array of digital switching modules (DSM), wherein each DMR has a transfer function such that a channel (p) in a time frame of (q) channels on an input line (r) appears on an output line (s) which is related to the input line by means of a backward rotate function, where s=MOD (q-r+p), where MOD=modulo q. This construction of switch ensures that all channels routed through the switch have one of only two possible values of whole frame time delay, thereby simplifying the setting up of a multislot connection.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: March 27, 1990
    Assignee: The Plessey Company plc
    Inventors: Thomas S. Maddern, Geoffrey Chopping
  • Patent number: 4905223
    Abstract: A wideband/multislot switching arrangement is provided for use in a digital telecommunications exchange. A call handling device is provided which receives signalling information about a path connection, and which communicates with a switch interface to generate a single switch request. The switch interface includes a map record of each circuit connection controlled by the call handling device and generates multiple switch requests which are used to control a number of switches to make the path connections.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: February 27, 1990
    Assignee: The Plessey Company plc
    Inventors: Richard J. Proctor, Thomas S. Maddern
  • Patent number: 4648090
    Abstract: The arrangement is for controlling speech communication in a communications exchange. The speech transmission is handled by a switchblock composed of a number of digital switching modules interconnected by a plurality of wire connections, and requiring the speech signals to be accompanied by bit and frame clock references to allow a receiving module to align the incoming data to its clock reference. The wire connections which carry frame synchronization information also carry control data which is bit interleaved with the frame synchronization information. Circuit means is provided which receives the bit interleaved frame synchronization information and control data, and demultiplexes the frame synchronization and control data to provide a retimed control data signal for use at the receiving module.
    Type: Grant
    Filed: February 1, 1985
    Date of Patent: March 3, 1987
    Assignee: The Plessey Company plc
    Inventors: Thomas S. Maddern, Alexander S. Philip
  • Patent number: 4587649
    Abstract: The method of growth of the digital switchblock is for use in telecommunications. The switchblock comprises a plurality of superplanes each including a plurality of central digital switching modules interconnected to a plurality of demultiplexer-mixer-remultiplexer stages; and, a plurality of outer digital switching modules connected to the demultiplexer-mixer-remultiplexer stages on each side of the superplanes. The outer digital switching modules are increased linearly as the number of telecommunication lines is increased from a first order of telecommunication lines. The number of superplanes is increased linearly as the number of telecommunication lines increase from the first order of telecommunication lines to a second order of telecommunication lines and thereafter remain constant as the number of lines increase.
    Type: Grant
    Filed: October 4, 1985
    Date of Patent: May 6, 1986
    Assignee: The Plessey Company plc
    Inventor: Thomas S. Maddern
  • Patent number: 4535442
    Abstract: A number of methods are used in the prior art to provide speech sample security in a duplicated switch plane telecommunications switching system and these fall into three categories; (i) use the switching planes in a main/standby mode with errors detected by a check code accompanying the speech sample on the plane in use detected errors cause the standby to be switched-to, (ii) transmit speech across both planes simultaneously and compare and (iii) as per (ii) accompanied by a check code to identify the plane at fault. Categories (i) and (iii) require "extra" routes to transmit the check code whereas category (ii) can not detect which sample is in error. In serial transmission switch planes there are no "spare" routes available without creating extra routes for the check code alone. The basic principle of the invention is to pass the speech through one plane only which is known as the "biased to" plane. A checkcode is passed through the other "biased from" plane.
    Type: Grant
    Filed: April 22, 1983
    Date of Patent: August 13, 1985
    Assignee: The Plessey Company plc
    Inventors: Thomas S. Maddern, John W. Ansell, Alexander S. Philip
  • Patent number: 4530089
    Abstract: The digital switchblock includes a plurality of processor clusters which communicate via peripheral interface buffers with a number of controllers connected in serial configuration and which further communicate with the switchblock. The switchblock has a number of receive digital switching modules connected to incoming PCM transmission channels and a number of transmit digital switching modules connected to outgoing PCM transmission channels. The receive and transmit digital switching modules are interconnected by way of a plurality of control digital switching modules, to which are connected all controllers. The interconnection between one receive digital switching module and one transmit digital switching module is set up by way of one central digital switching module by use of a plurality of control switch state maps stored in the controllers. The maps depict the current state of all digital switching modules and identify a connection path through the switchblock.
    Type: Grant
    Filed: July 26, 1983
    Date of Patent: July 16, 1985
    Assignee: The Plessey Company plc
    Inventors: John W. Ansell, Thomas S. Maddern, Alexander S. Philip
  • Patent number: 4425641
    Abstract: The digital switching module (DSM) is arranged as an LSI device providing digital (p.c.m.) switching for 256 channels in a space-time-space format. It is unidirectional in operation and is capable of switching data (digitally encoded speech) from any incoming channel to any outgoing channel. It is arranged to act as a building block in constructing larger digital switching networks. The DSM can be programmed to permit combinations of parallel or serial operation at input and output data interfaces, the mode being selected by the length of the pulse width of the frame start reference signal. The switching configuration of input channels to output channels is held within the DSM and can be amended by messages sent along a serial control interface. Interrogation of the switching state and of the data passing through the switch is provided by messages applied to an output control interface. The DSM can be arranged into square arrays to provide full availability switching for a greater number of channels.
    Type: Grant
    Filed: June 23, 1981
    Date of Patent: January 10, 1984
    Assignee: The Plessey Company plc
    Inventors: Joseph A. French, Thomas S. Maddern, Alexander S. Philip
  • Patent number: 4425640
    Abstract: It has been proposed to base advanced Digital Switching networks on a modular array using Digital Switch Modules (DSM). It has been found, for large traffic handling Digital switching systems, that the cross-office delay encountered in multi-stage networks based on 8.times.8 Digital Switching Modules (DSM's) is unacceptably large. To maintain the flexibility provided by the multi-stage concepts a demultiplexing/mixing/remultiplexing stage (DMR) is introduced to replace intermediate DSM ranks. The DMR is used to provide a preset time/space switching function within the total trunking providing the availability of a controlled stage but without the control and delay penalties associated with a fully flexible DSM or the control and link blocking disadvantages associated with a pure space switch. The DMR effectively acts as a pre-programmed or counter driven DSM.
    Type: Grant
    Filed: April 20, 1981
    Date of Patent: January 10, 1984
    Assignee: The Plessey Company plc
    Inventors: Alexander S. Philip, Thomas S. Maddern