Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A system and method for providing power from a source of stored electrical energy to a microcomputer for a user established "ride-through" period of time after a disruption in the primary power supply for the microcomputer. If the primary power supply is not restored within the ride-through time period the system performs an orderly shut down of computer applications. Should stored energy reserves run low during the primary power disruption, the system instead performs an abbreviated, critical application shut down. Following application shut down, or upon the expiration of a user established "shut down" time period, the system performs an orderly shut down of computer system operations and thereafter removes all power from the computer. Shut down and shut off procedures are canceled, if possible, upon restoration of the primary power supply.

Abstract: A field of scanned video pels is first broken up into cells representing small portions of characters to be recognized, according to a first set of logics. A second set of logics then recombines the cells into blocks containing individual characters separated from their neighbors.

Abstract: Control apparatus is responsive to CPU I/O commands for initiating chained I/O data transfers to cause virtual address translation (VAT) apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address in an I/O resolved address register reserved (unique) to the commanded I/O device connected to a shared I/O control unit and to repeat such an operation for each I/O device commanded by the CPU to do a data transfer and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into I/O resolved address registers shared for use by all of I/O devices whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer

Abstract: In a paged, virtual memory computer system an apparatus is provided for enabling I/O device adapters to request the CPU to allocate or resolve virtual pages into main storage pages as required for I/O data transfers. The I/O adapter provides the channel virtual address information specifying the requested page and channel function information which indicates whether the requested page is to be transferred from secondary storage into main storage or merely allocated as a page in main storage. The channel forms the virtual address information and the channel function information into a page request function event which is stored in an I/O event stack in main storage for retrieval and processing by the CPU.

Abstract: A monitor circuit for overseeing input/output activity in a digital computing system is disclosed. The circuit comprises a memory array for storing subchannel status words, each of which corresponds to an input/output operation unit. Each subchannel status word includes a timing monitor field having a current count subfield, a count limit subfield, and a command-in-progress bit position. Circuits are provided for incrementing at timed intervals numbers encoded in the current count subfields of those subchannel status words against which a request for an input/output operation is outstanding. A circuit is provided for comparing the numbers encoded in the current count subfields to the count limit subfields to determine if a response to a request for an input/output operation is overdue.