Patents by Inventor Thomas Trent
Thomas Trent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240395301Abstract: Technology is disclosed for a current source for reading a memory cell having a threshold switching selector. The current source may be operated in a first mode when turning on the threshold switching selector and in a second mode when sensing a voltage across the memory cell. The first mode may allow the use of the full range of the power supply voltage, which provides sufficient voltage across the memory cell to turn on the threshold switching selector. In the second mode the magnitude of the read current is less dependent on the voltage across the memory cell. The second mode therefore provides for accurate sensing of the memory cell. The first mode may also be used when writing the memory cell, which provides sufficient voltage across the memory cell to write the memory cell.Type: ApplicationFiled: July 27, 2023Publication date: November 28, 2024Applicant: Western Digital Technologies, Inc.Inventors: Christopher J. Petti, Ward Parkinson, Thomas Trent, James O'Toole
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Patent number: 12148459Abstract: Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.Type: GrantFiled: February 22, 2022Date of Patent: November 19, 2024Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Thomas Trent, Nathan Franklin, Michael Grobis, James W. Reiner, Hans Jurgen Richter, Michael Nicolas Albert Tran
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Patent number: 11971736Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.Type: GrantFiled: February 16, 2022Date of Patent: April 30, 2024Assignee: SanDisk Technologies LLCInventors: James O'Toole, Ward Parkinson, Thomas Trent
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Patent number: 11854592Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.Type: GrantFiled: May 31, 2022Date of Patent: December 26, 2023Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Publication number: 20230267981Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Applicant: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Thomas Trent, Nathan Franklin, Michael Grobis, James W. Reiner, Hans Jurgen Richter, Michael Nicolas Albert Tran
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Publication number: 20230259149Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.Type: ApplicationFiled: February 16, 2022Publication date: August 17, 2023Applicant: SanDisk Technologies LLCInventors: James O'Toole, Ward Parkinson, Thomas Trent
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Publication number: 20220293156Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.Type: ApplicationFiled: May 31, 2022Publication date: September 15, 2022Applicant: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Patent number: 11386945Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.Type: GrantFiled: October 2, 2020Date of Patent: July 12, 2022Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Patent number: 11328759Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.Type: GrantFiled: October 2, 2020Date of Patent: May 10, 2022Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Publication number: 20220108739Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Applicant: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Publication number: 20220108740Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Applicant: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Patent number: 11222678Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.Type: GrantFiled: October 2, 2020Date of Patent: January 11, 2022Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
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Patent number: 10373682Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.Type: GrantFiled: December 27, 2017Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Thomas Trent
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Publication number: 20190198106Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Applicant: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Thomas Trent
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Patent number: 10203032Abstract: A computer having a processor and memory that stores instructions executable by the processor, wherein the computer is programmed to: receive adaptive transmission clutch data from a plurality of first vehicles, the data from each first vehicle including a modified shifting profile; determine, using the received data, an updated initial shifting profile; and provide the updated initial profile to a plurality of second vehicles.Type: GrantFiled: March 21, 2017Date of Patent: February 12, 2019Assignee: FORD MOTOR COMPANYInventors: Charles Ernest Gray, Donald G. Levens, Gurjeet Singh, Douglas Ryan Cecil, Matthew Thomas Trent
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Publication number: 20180274668Abstract: A computer having a processor and memory that stores instructions executable by the processor, wherein the computer is programmed to: receive adaptive transmission clutch data from a plurality of first vehicles, the data from each first vehicle including a modified shifting profile; determine, using the received data, an updated initial shifting profile; and provide the updated initial profile to a plurality of second vehicles.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Applicant: Ford Motor CompanyInventors: Charles Ernest Gray, Donald G. Levens, Gurjeet Singh, Douglas Ryan Cecil, Matthew Thomas Trent
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Patent number: 10036433Abstract: A continuously variable transmission includes a first shaft driveably connected to a power-plant and having a first pair of sheave disks, and a second shaft having a second pair of sheave disks. A tension member is connected to the first and second pairs of disks such that power is transmittable between the first and second shafts. A third shaft is selectively driveably connected to the second shaft via a clutch. The clutch includes an inner race fixed to one of the second and third shafts, and an outer race fixed to a gear and having an inner surface circumscribing the inner race. At least one pawl is biased to couple the races in a fixed relationship for common rotation. The clutch further includes an electric coil and an armature configured to engage the pawl to decouple the races in response to current being supplied to the electric coil.Type: GrantFiled: June 14, 2016Date of Patent: July 31, 2018Assignee: Ford Global Technologies, LLCInventors: James Trent, Norman Jerry Bird, Matthew Thomas Trent
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Publication number: 20170356507Abstract: A continuously variable transmission includes a first shaft driveably connected to a power-plant and having a first pair of sheave disks, and a second shaft having a second pair of sheave disks. A tension member is connected to the first and second pairs of disks such that power is transmittable between the first and second shafts. A third shaft is selectively driveably connected to the second shaft via a clutch. The clutch includes an inner race fixed to one of the second and third shafts, and an outer race fixed to a gear and having an inner surface circumscribing the inner race. At least one pawl is biased to couple the races in a fixed relationship for common rotation. The clutch further includes an electric coil and an armature configured to engage the pawl to decouple the races in response to current being supplied to the electric coil.Type: ApplicationFiled: June 14, 2016Publication date: December 14, 2017Inventors: James TRENT, Norman Jerry BIRD, Matthew Thomas TRENT
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Patent number: 9738286Abstract: A vehicle including a continuously variable transmission including a gear selectively locked to an output shaft via a clutch actuated by an electric coil. The vehicle also includes a controller configured to, in response to wheel hop being detected, energize the coil to disengage the clutch allowing the gear and the output shaft to rotate independently of each other.Type: GrantFiled: June 14, 2016Date of Patent: August 22, 2017Assignee: Ford Global Technologies, LLCInventors: James Trent, Norman Jerry Bird, Matthew Thomas Trent
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Patent number: 9657783Abstract: A clutch module for a dual clutch transmission (DCT) is designed to improve circumferential fluid distribution to reduce or eliminate an unpleasant noise during engagement. In some embodiments, the reaction plate is restrained in a position offset 1-3 degrees from perpendicular to the housing axis. Consequently, 0.2-0.7 mm of clearance remains on one radial side of the clutch when all clearance has been removed on the other radial side of the clutch. Relative rotation between the hub and the housing pushes fluid from the tight side toward the loose side. In an alternative embodiment, the piston is designed to orient the pressure plate non-perpendicular to the housing axis.Type: GrantFiled: January 20, 2015Date of Patent: May 23, 2017Assignee: Ford Global Technologies, LLCInventors: Matthew Thomas Trent, George Frederick MacDonald, Bryant David Grytzelius