Abstract: A numerically controlled oscillator (NCO) is arranged to accumulate control values for each transition of a system clock to provide an accumulation signal and an edge signal. A speed multiplier value (N) is selected to simulate a desired clock resolution of N times the system clock resolution. The multi-phase predictive clock circuit is arranged to provide clock phase output signals that each correspond to a predicted clock phase as if the system clock where running at N times faster than the actual system clock. The edge detector circuit is arranged to compare values of adjacent clock phases to identify a transition in one of the clock phases. The phase encoder circuit is arranged to provide a phase signal that indicates a transition in one clock phase. The edge signal and the phase signal can be used for careful phase alignment control at effectively higher resolution.

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

Abstract: A differential amplifier circuit achieves offset cancellation by supplying an offset correction current from a current copier circuit to the output of the differential amplifier. The current copier is programmed by closing a first switch to short the differential input terminals of the amplifier, by opening a second switch to break the feedback loop of the amplifier, and by closing a third switch to allow the current copier to sense the offset output voltage at the output of the amplifier. The current copier generates an equal and opposite offset cancellation current which is summed with the offset current from the amplifier. The current copier circuit includes a storage capacitor for storing a voltage required to produce such offset cancellation current. After programming the storage capacitor, the third switch is opened, the first switch is opened, and the second switch is closed for normal operation.

Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by providing each input signal as dual input signals that track each other within two different voltage ranges. A shield voltage is provided approximately midway between the uppermost and lowermost power supply voltages. The first input signal ranges between the lowermost power supply voltage and the shield voltage, and the second input signal ranges between the shield voltage and the uppermost power supply voltage. The first and second input signals drive the gates of n-channel and p-channel CMOS switching transistors, respectively, the drain terminals of which are coupled to first and second output terminals, respectively. N-channel and p-channel shield transistors are connected in series between the first and second output terminals, and have their gate terminals coupled to the shield voltage.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: An integrated circuit is provided for generating analog output voltages for a series of column driver output circuits used to drive an active or passive matrix LCD display. The digital value corresponding to the shade of gray for each column is stored on the integrated circuit. A shift register is clocked to sequentially enable tap points of a resistive divider network for providing four monotonically increasing analog voltages on each shift register clock cycle. A binary counter is clocked along with the shift register, and the more significant bits of the stored digital value for each column driver output circuit are each compared with the current binary count to detect a correlation. Upon detecting a correlation, the two least significant bits of the stored digital value for each column driver circuit are used to select one of the four analog voltages during the current counter cycle, and the selected analog value is sampled and held for driving a column of the LCD display.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: A compensation circuit equalizes processing (speed) differences between driver chips used to drive an active matrix LCD display by inserting a delay in opposite proportion to the speed of the driver IC so that a faster IC will receive a longer delay and a slower IC will receive a shorter delay.