Patents by Inventor Thomas W. Williams

Thomas W. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6950974
    Abstract: Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: September 27, 2005
    Assignee: Synopsys Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Thomas W. Williams
  • Patent number: 6807646
    Abstract: A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: October 19, 2004
    Assignee: Synopsys, Inc.
    Inventors: Thomas W. Williams, Peter Wohl, John A. Waicukauski, Rohit Kapur
  • Patent number: 6766501
    Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types, skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: July 20, 2004
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Rohit Kapur, Thomas W. Williams
  • Patent number: 6631344
    Abstract: In a computer implemented synthesis system, a method of generating a test pattern for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving a netlist specification representing a design to be realized in physical form and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the simulation instantiated within the synthesis system, deterministic test pattern generation is performed to obtain a first portion (partial) of a test pattern. The test pattern is operable to detect a fault in the circuit netlist once speculative test pattern generation is performed to obtain a remaining portion of the test pattern. The first portion and the remaining portion of the test pattern comprise a test vector operable to detect the fault when used with automated test equipment for testing a device resulting from the design.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: October 7, 2003
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Thomas W. Williams
  • Patent number: 6615380
    Abstract: According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. The scan chain is transformed by the test synthesis tool of the present invention into dynamic scan chains with the addition of reconfiguration circuitry. The reconfiguration circuitry partitions the scan chain into multiple segments and enables each segment to be selectively “bypassed” (or deactivated) during test application. Shorter test patterns that are only pertinent to one or more segments are necessary, resulting in a reduction in overall test data volume and test application time. The present invention also provides a modified ATPG technique for generating test patterns for the dynamic scan chains.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: September 2, 2003
    Assignee: Synopsys Inc.
    Inventors: Rohit Kapur, Denis Martin, Thomas W. Williams
  • Patent number: 6453437
    Abstract: A method for generating a test pattern for use in testing an integrated circuit device. The computer implemented steps of receiving and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the netlist simulation, a set of circuit paths for each fault of the plurality of faults within the netlist specification is determined. From this set of paths, respective longest paths for each fault is determined. Using an ATPG (automatic test pattern generation) process, a test vector is determined for the first fault. Transition fault simulation is then performed on the first fault by applying the test vector to a first path through the first fault, wherein the first path is the longest path traversing through the first fault as determined by the ATPG process.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: September 17, 2002
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Thomas W. Williams, John Waicukauski, Peter Wohl
  • Patent number: 6434733
    Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: August 13, 2002
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Rohit Kapur, Thomas W. Williams
  • Publication number: 20020093356
    Abstract: A method and circuit for testing an integrated circuit device using intelligent test vector formatting that reduces the storage required for test patterns and also provides encryption of the test patterns. A first memory stores a test vector mask that is a sequence of bits to indicate if corresponding test vector data is deterministic or random. The test vector data contains a portion that is deterministically generated by automatic test pattern generation (ATPG) software and a portion that is random. A second memory contains a sequence of bits that represent the deterministic test vector data. A random number generator (e.g., linear feed-back shift register, LFSR) generates a reproducible sequence of pseudo random bits that is based on a seed value. A selector circuit is used to select bits either from the second memory or from the random number generator based on the value of the mask vector. The output of the selector provides a fully specified test vector for application to the device under test (DUT).
    Type: Application
    Filed: November 30, 2000
    Publication date: July 18, 2002
    Inventors: Thomas W. Williams, Rohit Kapur, Anthony Taylor
  • Patent number: 6405355
    Abstract: A computer implemented method of constructing a scan chain. According to the present invention, scan cells are inserted into a netlist description of an integrated circuit design and are coupled serially together to form a scan chain. The resulting netlist is then passed to layout processes where the cells of the integrated circuit design are automatically placed and routed. The layout processes are performed without regard to any predetermined constraints designating any particular functional pins of the netlist design as scan-in or scan-out ports for the scan chain. After the cells are placed, a first functional pin is selected as the scan-in port and a second functional pin is selected as the scan-out port according to cell placement information. In particular, the functional pin that is closest to the leading scan cell is selected as the scan-in port. The functional pin that is closest to the last scan cell is selected as the scan-out port for the scan chain.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: June 11, 2002
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Rohit Kapur, Thomas W. Williams
  • Patent number: 6385750
    Abstract: A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: May 7, 2002
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Thomas W. Williams, John Waicukauski, Peter Wohl
  • Patent number: 5184141
    Abstract: A structurally-embedded electronics assembly is disclosed and includes an outer skin member which is lightly loaded structurally, a primary load-carrying member positioned inboard from the outer skin member, a core member positioned between the primary load-carrying member and the outer skin member, an intermediate skin member positioned between the outer skin member and the core member and an electronics structure positioned between a predetermined two of the members or intermingled with a predetermined number of the members set forth above which are adjacent each other. In another embodiment, a thermally conductive baseplate member is positioned inboard from the primary load-carrying member. In another embodiment, a vibration damping member is positioned inboard from the primary load-carrying member.
    Type: Grant
    Filed: April 5, 1990
    Date of Patent: February 2, 1993
    Assignee: Vought Aircraft Company
    Inventors: Jerome J. Connolly, Michael D. Barrick, William L. D'Agostino, Gerald F. Thomas, Thomas W. Williams
  • Patent number: 4865192
    Abstract: An improvement for a golf bag is disclosed wherein the improvement comprises an adjustable internal supporting apparatus having a retractable spike for standing a golf bag upright on the ground which apparatus also provides general longitudinal support of the golf bag. The apparatus has a central shaft between a club separator attached to the top collar of a golf bag having flexible sides and the bottom collar at the base of the bag. A hollow tube sliding within the shaft bears a solid spike threaded to its lower end for sticking in the ground and a handle threaded to its upper end. The upper end of the shaft is guided by a hole in the club separator; the lower end is guided by a hole in a cup attached to the bottom collar of the golf bag. A spring, one end of which is clipped to the upper end of the inside of the shaft, the other end inserted into a hole in the side of the hollow tube, is stretched by downward pressure from the hand on the tube handle.
    Type: Grant
    Filed: May 10, 1988
    Date of Patent: September 12, 1989
    Assignee: Sports Specialties, Inc.
    Inventor: Thomas W. Williams
  • Patent number: 4726023
    Abstract: A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities of fault exposure is calculated for a modified system with the memory portion removed, with its inputs directly connected to its outputs. This probability can be related, by provided relations, to upper and lower bounds of the fault exposure in the unmodified system. The relationships rely upon how the logic portions process given test vectors to control the unremoved memory portion.
    Type: Grant
    Filed: May 14, 1986
    Date of Patent: February 16, 1988
    Assignee: International Business Machines Corporation
    Inventors: John L. Carter, Leendert M. Huisman, Thomas W. Williams
  • Patent number: 4655436
    Abstract: A heat recovery and storage system for use in connection with a melting furnace. In such system, heat from the exhaust gas of a melting furnace is recovered and used to preheat scrap metal and to maintain such preheated scrap metal in its preheated form until it is charged into the melting furnace.
    Type: Grant
    Filed: December 10, 1985
    Date of Patent: April 7, 1987
    Inventor: Thomas W. Williams
  • Patent number: 4509008
    Abstract: Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly.
    Type: Grant
    Filed: April 10, 1984
    Date of Patent: April 2, 1985
    Assignee: International Business Machines Corporation
    Inventors: Sumit DasGupta, Matthew C. Graf, Robert A. Rasmussen, Thomas W. Williams
  • Patent number: 4503386
    Abstract: Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly.
    Type: Grant
    Filed: April 20, 1982
    Date of Patent: March 5, 1985
    Assignee: International Business Machines Corporation
    Inventors: Sumit DasGupta, Matthew C. Graf, Robert A. Rasmussen, Thomas W. Williams
  • Patent number: 4293919
    Abstract: One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out.
    Type: Grant
    Filed: August 13, 1979
    Date of Patent: October 6, 1981
    Assignee: International Business Machines Corporation
    Inventors: Sumit Dasgupta, Prabhakar Goel, Thomas W. Williams
  • Patent number: 4277699
    Abstract: A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a `D` type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
    Type: Grant
    Filed: July 26, 1979
    Date of Patent: July 7, 1981
    Assignee: International Business Machines Corporation
    Inventors: David J. Brown, Ronald G. Walther, Thomas W. Williams, Michael D. Wrigglesworth