Patents by Inventor Thomas Walter Keller, Jr.
Thomas Walter Keller, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9009503Abstract: A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit.Type: GrantFiled: July 5, 2012Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Malcolm Scott Allen-Ware, Wael El-Essawy, Alexandre Peixoto Ferreira, Thomas Walter Keller, Jr., Karthick Rajamani, Juan Carlos Rubio
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Patent number: 8850240Abstract: A method for relating a data processing system with a power branch circuit is provided in the illustrative embodiments. A second signal is combined with a power signal to form a combination signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. The second signal is synchronized with the modulating signal in the power signal. A determination is made whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period. Responsive to the determining being affirmative, the data processing system is related with the power branch circuit.Type: GrantFiled: April 30, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Malcolm Scott Allen-Ware, Wael R El-Essawy, Alexandre Peixoto Ferreira, Thomas Walter Keller, Jr., Juan Carlos Rubio
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Publication number: 20140013126Abstract: A method, system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. Each signal in a set of signals is combined with a power signal to form a set of combination signals, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. An amplitude of a corresponding signal in each combined signal in the set of combined signals is determined over a period. Using a discriminating logic, a determination is made whether the modulating signal is present in the power signal. Responsive to the discriminating logic producing an affirmative result, the data processing system is related with the power branch circuit.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Malcolm Scott Allen-Ware, Wael El-Essawy, Alexandre Peixoto Ferreira, Thomas Walter Keller, JR., Karthick Rajamani, Juan Carlos Rubio
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Publication number: 20130054999Abstract: A method for relating a data processing system with a power branch circuit is provided in the illustrative embodiments. A second signal is combined with a power signal to form a combination signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. The second signal is synchronized with the modulating signal in the power signal. A determination is made whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period. Responsive to the determining being affirmative, the data processing system is related with the power branch circuit.Type: ApplicationFiled: April 30, 2012Publication date: February 28, 2013Inventors: MALCOLM SCOTT ALLEN-WARE, Wael R. El-Essawy, Alexandre Peixoto Ferreira, Thomas Walter Keller, JR., Juan Carlos Rubio
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Publication number: 20130054993Abstract: A system, and computer program product for relating a data processing system with a power branch circuit are provided in the illustrative embodiments. A second signal is combined with a power signal to form a combination signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. The second signal is synchronized with the modulating signal in the power signal. A determination is made whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period. Responsive to the determining being affirmative, the data processing system is related with the power branch circuit.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Malcolm Scott Allen-Ware, Wael R. El- Essawy, Alexandre Peixoto Ferreira, Thomas Walter Keller, JR., Juan Carlos Rubio
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Patent number: 8140868Abstract: A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.Type: GrantFiled: August 14, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Wesley Michael Felter, Thomas Walter Keller, Jr., Karthick Rajamani, Cosmin Rusu
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Patent number: 8010764Abstract: A method and system for decreasing power consumption in memory arrays having usage-driven power management provides decreased power consumption in the memory array of a processing system. Per-page usage information is gathered on memory by a memory controller and periodically evaluated by software. The software distinguishes between more frequently accessed pages and less frequently accessed pages by analyzing the gathered usage information and periodically migrates physical memory pages in order to group less frequently accessed pages and more frequently access pages in separately power-managed memory ranks. When used in conjunction with a usage-driven power management mechanism, the ranks containing the less frequently accessed pages can enter deeper power-saving states and/or any power-saving state for longer periods.Type: GrantFiled: July 7, 2005Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Thomas Walter Keller, Jr., Charles R. Lefurgy, Hai Huang
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Patent number: 7921313Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.Type: GrantFiled: April 17, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Soraya Ghiasi, Thomas Walter Keller, Jr., Ramakrishna Kotla, Freeman Leigh Rawson, III
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Patent number: 7752470Abstract: A method and system for power management including device controller-based device use evaluation and power-state control provides improved performance in a power-managed processing system. Per-device usage information is measured and evaluated during process execution and is retrieved from the device controller upon a context switch, so that upon reactivation of the process, the previous usage evaluation state can be restored. The device controller can then provide for per-process control of attached device power management states without intervention by the processor and without losing the historical evaluation state when a process is switched out. The device controller can control power-saving states of connected devices in conformity with the usage evaluation without processor intervention and across multiple process execution slices. The device controller may be a memory controller and the controlled devices memory modules or banks within modules if individual banks can be power-managed.Type: GrantFiled: December 3, 2003Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Hai Huang, Thomas Walter Keller, Jr., Eric Van Hensbergen
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Publication number: 20080301475Abstract: A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.Type: ApplicationFiled: August 14, 2008Publication date: December 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: WESLEY MICHAEL FELTER, Thomas Walter Keller, JR., Karthick Rajamani, Cosmin Rusu
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Patent number: 7444526Abstract: A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.Type: GrantFiled: June 16, 2005Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Wesley Michael Felter, Thomas Walter Keller, Jr., Karthick Rajamani, Cosmin Rusu
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Patent number: 7386739Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.Type: GrantFiled: May 3, 2005Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Soraya Ghiasi, Thomas Walter Keller, Jr., Ramakrishna Kotla, Freeman Leigh Rawson, III
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Patent number: 7197652Abstract: A method and system for energy management in a simultaneous multi-threaded (SMT) processing system including per-thread device usage monitoring provides control of energy usage that accommodates thread parallelism. Per-device usage information is measured and stored on a per-thread basis, so that upon a context switch, the previous usage evaluation state can be restored. The per-thread usage information is used to adjust the thresholds of device energy management decision control logic, so that energy use can be managed with consideration as to which threads will be running in a given execution slice. A device controller can then provide for per-thread control of attached device power management states without intervention by the processor and without losing the historical evaluation state when a process is switched out. The device controller may be a memory controller and the controlled devices memory modules or banks within modules if individual banks can be power-managed.Type: GrantFiled: December 22, 2003Date of Patent: March 27, 2007Assignee: International Business Machines CorporationInventors: Thomas Walter Keller, Jr., Eric Van Hensbergen
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Patent number: 6836849Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.Type: GrantFiled: April 5, 2001Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Bishop Chapman Brock, Harm Peter Hofstee, Mark A. Johnson, Thomas Walter Keller, Jr., Kevin John Nowka
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Patent number: 6772199Abstract: A method and system for enhanced cache efficiency is a cache associated with a server in a wide area network having multiple servers and clients. Objects retrieved from the network by a server are stored within a cache associated with the server and selected objects are designated as temporarily exempt from replacement based upon a preselected criterion, such as size or mandated quality of service for the client which requested the object. After the cache is full or nearly full, subsequently retrieved objects are stored by casting out one or more objects which are not exempt from replacement according to a specified replacement algorithm, such as Least Recently Utilized, or by casting out any object or objects, if all objects in the cache are designated as exempt from replacement.Type: GrantFiled: September 14, 2000Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Thomas Walter Keller, Jr., Karthikeyan P. Sankaralingam