Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.

Abstract: Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.

Abstract: Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.

Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.

Abstract: Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.

Abstract: A process for producing low-density, porous silica films in a vacuum environment is provided. The films are advantageous for use as low dielectric constant insulating materials in semiconductor devices. In a first step, an organic-group-containing silica precursor is deposited on a semiconductor substrate in a chemical vapor deposition reactor. In a second step, the organic groups are removed by heating in a furnace in an oxidizing environment or by exposure to an oxidizing plasma, thereby creating a low density silica film.

Abstract: An interlevel dielectric stack for use in semiconductor devices is provided. The interlevel stack includes a bottom adhesion layer, a middle layer composed of a fluorinated amorphous carbon film, and a top adhesion layer. The bottom and top adhesion layers are composed of a silicon carbide material containing hydrogen. The dielectric stack is subjected to rigorous adhesion and thermal testing. A single continuous process for depositing the dielectric stack in a high density plasma reactor is also provided.

Abstract: An interlevel dielectric stack for use in semiconductor devices is provided. The interlevel stack includes a bottom adhesion layer, a middle layer composed of a fluorinated amorphous carbon film, and a top adhesion layer. The bottom and top adhesion layers are composed of a silicon carbide material containing hydrogen. The dielectric stack is subjected to rigorous adhesion and thermal testing. A single continuous process for depositing the dielectric stack in a high density plasma reactor is also provided.

Abstract: A process for producing low-density, porous silica films in a vacuum environment is provided. The films are advantageous for use as low dielectric constant insulating materials in semiconductor devices. In a first step, an organic-group-containing silica precursor is deposited on a semiconductor substrate in a chemical vapor deposition reactor. In a second step, the organic groups are removed by heating in a furnace in an oxidizing environment or by exposure to an oxidizing plasma, thereby creating a low density silica film.