Patents by Inventor Tien Fan Ou

Tien Fan Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899538
    Abstract: The present invention provides a non-volatile memory device, including a source region and a drain region, a channel region, a floating gate, an enhance hot carrier (hole or electron) injection gate and an erasing gate. The floating gate is disposed on the channel region and the source region and a first dielectric layer is disposed therebetween. The enhance hot carrier injection gate is disposed on the floating gate and the substrate wherein the enhance hot carrier injection gate has an L-shape cross-section. A second dielectric layer is disposed between the enhance hot carrier injection gate and the floating gate, and a fourth dielectric layer is disposed between the enhance hot carrier injection gate and the substrate. The erasing gate is disposed on the drain region. A third dielectric layer is disposed between the erasing gate and the substrate.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Lung Chang, Tien-Fan Ou
  • Patent number: 9773554
    Abstract: An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 26, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Lee, Tien-Fan Ou, Jyun-Siang Huang, Chien-Hung Liu
  • Publication number: 20150279468
    Abstract: An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 1, 2015
    Applicant: Macronix International Co., Ltd.
    Inventors: CHIH-WEI LEE, TIEN-FAN OU, JYUN-SIANG HUANG, CHIEN-HUNG LIU
  • Patent number: 8369148
    Abstract: An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: February 5, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai, Jyun-Siang Huang
  • Patent number: 8218364
    Abstract: An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N?1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 10, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Patent number: 8143665
    Abstract: The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: March 27, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou
  • Patent number: 8139416
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: March 20, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Publication number: 20120002484
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Application
    Filed: June 13, 2011
    Publication date: January 5, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: LIT-HO CHONG, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Publication number: 20110242891
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Application
    Filed: June 13, 2011
    Publication date: October 6, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: LIT-HO CHONG, WEN-JER TSAI, TIEN-FAN OU, JYUN-SIANG HUANG
  • Patent number: 7995384
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: August 9, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai, Jyun-Siang Huang
  • Patent number: 7974127
    Abstract: A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: July 5, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Publication number: 20110079840
    Abstract: A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 7, 2011
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou, Cheng-Hsien Cheng
  • Patent number: 7864594
    Abstract: A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 4, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Patent number: 7795673
    Abstract: A manufacturing method of a vertical non-volatile memory is provided. A first semiconductor layer, a first barrier, a second semiconductor layer, a second barrier and a third semiconductor layer are formed on a substrate sequentially. The first and the third semiconductor layers have a first conductive state, while the second semiconductor layer has a second conductive state. Several strips of active stacked structures are formed by removing portions of the first, second and third semiconductor layers, and portions of the first and second barrier on the substrate. After forming a storage structure on the substrate, the storage structure is covered with a conductive layer filling spaces among the active stacked structures. A portion of the conductive layer is removed to form word lines across the active stacked structures.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: September 14, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai
  • Patent number: 7768825
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: August 3, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsuan Ling Kao, Wen Jer Tsai, Tien Fan Ou
  • Publication number: 20100176437
    Abstract: The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai, Tien-Fan Ou
  • Patent number: 7723757
    Abstract: A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: May 25, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien Fan Ou, Wen-Jer Tsai, Hsuan Ling Kao, Yi Ying Liao
  • Publication number: 20100039867
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Applicant: Macronix International Co., Ltd.
    Inventors: Tien-Fan Ou, Wen-Jer Tsai, Jyun-Siang Huang
  • Publication number: 20090116284
    Abstract: A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.
    Type: Application
    Filed: October 14, 2008
    Publication date: May 7, 2009
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Publication number: 20090116287
    Abstract: An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.
    Type: Application
    Filed: November 4, 2008
    Publication date: May 7, 2009
    Applicant: Macronix International Co., Ltd.
    Inventors: TIEN-FAN OU, Wen-Jer Tsai, Jyun-Siang Huang