Abstract: A pattern matching method is disclosed. The method includes following steps. A character is searched in a skip table of a pattern such that a flag value and a skip value are returned. The sliding window is shifted according to the skip value when the flag value indicates the character is not a pattern end. The character plus at least one byte preceding the character is hashed when the flag value indicates the character is the pattern end such that a character hashing value is returned. A pattern end portion is hashed, wherein the size of the pattern end portion is equal to the size of the character plus the size of the byte such that a pattern hashing value is returned. The character hashing value is compared with the pattern hashing value. An exact matching process is performed when the character hashing value is equal to the pattern hashing value.

Abstract: The present invention uses a swing structure to avoid using a clock period at a non-efficient execution time. The execution time is precisely controlled to enhance a performance of a processor using a low voltage. Thus, synchronization problems in a chip under different environments are solved for high reliability.

Abstract: A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. The present invention provides multiple data transfer in parallel between multiple processor cores or multiple function units and register banks with dynamic configuration. The present invention thus obtains a low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity and a simplified circuit.

Abstract: With the present invention, buses and silicon IPs are simulated together. A virtual platform is provided for designing hardware and system. And correct and fast simulations of I/Os are provided through the I/Os on a FPGA. Thus, software performances are monitored and system bottlenecks are acquired.

Abstract: The present invention discloses a multi-core SOC synchronization component, which comprises a key administration module, a thread schedule unit supporting data synchronization and thread administration, and an expansion unit serving to expand the memory capacity of the key administration module. The present invention can improve interconnect traffic and prevents from interconnect blocking. The present invention can function as a standard interface of different components. Thus, the present invention can solve the synchronization problem and effectively accelerate product design.

Abstract: An exemplary protection circuit includes a protecting unit for protecting the protection circuit, a detecting unit electrically connected to the protecting unit, and a processor. The detecting unit is configured for detecting whether water enters into the detecting unit or not, and outputting a detecting result. The processor is electrically connected to the protecting unit and the detecting unit, and controls the protecting unit to turn on or cut off in response to the detecting result.

Abstract: A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected to a group of CAM cells. The dual-ported dynamic circuit includes a setting circuit, a first directing circuit, a second directing circuit, a first AND dynamic output circuit and a second AND dynamic output circuit.

Abstract: A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected to a group of CAM cells. The dual-ported dynamic circuit includes a setting circuit, a first directing circuit, a second directing circuit, a first AND dynamic output circuit and a second AND dynamic output circuit.

Abstract: An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.

Abstract: A cooperative multithreading architecture includes an instruction cache, capable of providing a micro-VLIW instruction; a first cluster, connects to the instruction cache to fetch the micro-VLIW instruction; and a second cluster, connects to the instruction cache to fetch the micro-VLIW instruction and capable of execution acceleration. The second cluster includes a second front-end module, connects to the instruction cache and capable of requesting and dispatching the micro-VLIW instruction; a helper dynamic scheduler, connects to the second front-end module and capable of dispatching the micro-VLIW instruction; a non-shared data path, connects to the second front-end module and capable of providing a wider data path; and a shared data path, connected to the helper dynamic scheduler and capable of assisting a control part of the non-shared data path. The first cluster and the second cluster carry out execution of the respective micro-instructions in parallel.

Abstract: A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

Abstract: A multiple skip structure of a pattern matcher uses a shift engine to read a string and divide the string into a front module and a rear module. The shift engine uses the rear module of the string to index the shift index column of a shift table and retrieves a corresponding shift value and signature value back to the shift engine. The shift engine uses the shift value for the first level of filtering. If the shift value indicates a pattern is contained, it then compares a signature value with a shift hash value for a second level of filtering. The shift hash value is obtained from using the front module of the string via a hash function. If the shift hash value equals to the signature value, then it transmits the position of the string to a trie engine for a full pattern matching.

Abstract: An apparatus and method of providing flexible load and store for multimedia applications are provided by the present invention, which comprising a register file, a load and store unit, a memory, a selective maskable permutable and collector load module (SMPCKM), and a control unit. The load and store unit includes a selective permutable and scatter store module (SPSSM), which can perform selective, permutable, and scatter store operation. Driving control signals by the control unit to control the operation state. With the present invention, permuting data could be efficient. The source data could be permuted arbitrarily with different operation modes according to the load and store characteristic, and then stored the source data to destination location. Moreover, the use of the load and store unit can reduce burden of performing permutable operation which needs extra instructions, such that performance can be enhanced.

Abstract: An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical operation, under the control of a control unit. By configuring the auxiliary computing units along the data path, additional processing to the operands could be carried out within the same instruction cycle. As such, a processing unit incorporating such an arithmetic and logic device is able to achieve significant performance improvement both in terms of code size and memory access overhead.

Abstract: The present invention is a bulk preload and poststore technique system and method applied on a unified advanced VLIW (Very Long Instruction Word) DSP (Digital Signal Processor), specifically the system and method for exchanging data between register files that works in a VLIW architecture. The method of the present invention comprises: an iteration of the prolog; an iteration of the loop body; and an iteration of the epilog. The system of the present invention comprises: a bulk memory access controller; a buffer register file; a switching module; and a registered file switch controller.

Abstract: The present invention discloses a power-efficient encoder architecture for address stream on bus and a power-efficient encoding method for address stream on bus. In the design of the encoder architecture, a encoder is installed on the path along which the address stream flows from the central processing unit to a bus, and another encoder is installed on the path along which the address stream flows from the bus to a memory, and the aforementioned encoders all have the encode/decode function.

Abstract: The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).

Abstract: A method for fabricating polycrystalline silicon film transistors, which includes a polysilicon spacer capping onto a sidewall of an active layer in the thin film transistors by an isotropic dry etching of the silicon film. This method suppresses the shrinkage of the active layer during recrystallization by the laser. Large grains are formed in the channel after recrystallization utilizing a high-energy continuous wavelength laser or an excimer laser annealing the active layer. This process does not require an additional mask. Uniform arrangement of grain boundaries and large grain sizes promotes uniformity of performance of the device, which is important in the fields of low temperature polycrystalline silicon thin film transistors (LTPS-TFTs).

Abstract: Disclosed is “System and Method for Digital Content Rights Management on Portable Storage Devices.” Due to the fact that digital content will some become the master industry in the future, a new usage rights management is needed, especially for those storage media such as portable PDA or handy flash. In conventional methods, the network has to be kept alive for determining the license validation. Conversely, the new method only needs to connect to Internet when downloading the digital content that was chosen. The digital content with personal identification and usage rights are encrypted. Henceforth, the digital content is prevented from illegal usage such as copy and unauthorized read. By the usage rights management, several kinds of limitations are defined for being operated in combination with each other, to generate various usage permissions while the overall system is easily managed. This invention is platform independent and suitable for different kinds of portable storage devices.

Abstract: The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).