Patents by Inventor Tien-I Bao

Tien-I Bao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279896
    Abstract: Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Sunil Kumar Singh, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10408998
    Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20190252249
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20190252346
    Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Publication number: 20190219762
    Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10353147
    Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10354954
    Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Patent number: 10332838
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10312139
    Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
  • Patent number: 10312136
    Abstract: Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sunil Kumar Singh, Chung-Ju Lee, Tien-I Bao
  • Publication number: 20190164848
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a first insulation material layer in a portion of a trench between a first protruding structure and a second protruding structure over a substrate and performing a pre-treatment process on the first insulation material layer. The method further includes performing a first insulation material conversion process on the first insulation material layer and forming a second insulation material layer covering the first insulation material layer in the trench. In addition, a first distance between upper portions of the first protruding structure and the second protruding structure before performing the first insulation material conversion process is different from a second distance between the upper portions of the first protruding structure and the second protruding structure after performing the first insulation material conversion process.
    Type: Application
    Filed: July 27, 2018
    Publication date: May 30, 2019
    Inventors: Han-Pin CHUNG, Chih-Tang PENG, Tien-I BAO
  • Publication number: 20190164748
    Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.
    Type: Application
    Filed: April 3, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia Cheng CHOU, Li Chun TE, Po-Cheng SHIH, Tien-I BAO
  • Publication number: 20190148514
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Publication number: 20190146165
    Abstract: A method of making an optical bench includes forming a trench in a substrate and wherein the trench has a sloping side, forming a reflector layer over the sloping side, depositing a redistribution layer over the substrate, disposing an under bump metallization (UBM) layer over the redistribution layer, depositing a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer, and mounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate. The reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Inventors: Wan-Yu LEE, Chun-Hao TSENG, Hai-Ching CHEN, Tien-I BAO
  • Patent number: 10290536
    Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Publication number: 20190131240
    Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20190131436
    Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-En Cheng, Chun-Te Li, Kai-Hsuan Lee, Tien-I Bao, Wei-Ken Lin
  • Publication number: 20190123204
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 10269567
    Abstract: A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Teng-Chun Tsai, Yung-Cheng Lu, Ying-Tsung Chen, Tien-I Bao
  • Patent number: 10269757
    Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao