Patents by Inventor Tien-Wei YU
Tien-Wei YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220027300Abstract: A USB hub device having functionality of self firmware updating is disclosed. The USB hub device is integrated in a host electronic system, and comprises an upstream port, a plurality of downstream ports and a hub module comprising a plurality of second USB controller units. On the other hand, the host electronic system has a second USB controller unit. After one electronic device is coupled to one downstream port, the first USB controller unit sends a detection signal for verifying whether the electronic device includes at least one firmware update data or not. In case of the electronic device being verified to have the firmware update data, the hub module transmit the firmware update data from the electronic device to a memory unit thereof, thereby completing a firmware update of the USB hub device.Type: ApplicationFiled: January 20, 2021Publication date: January 27, 2022Applicant: PROLIFIC TECHNOLOGY INC.Inventors: TIEN-WEI YU, CHENG-SHENG CHAN, CHUN-SHIU CHEN
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Patent number: 11216401Abstract: A host-to-host chip includes: first and second ports coupled to first and second hosts respectively; and a host-to-host control circuit coupled to the first port and the second port. When the host-to-host chip is coupled to the second host, the host-to-host control circuit identifies whether the second host is an i-Phone or an Android smartphone. If the host-to-host control circuit identifies that the second host is an i-Phone smartphone, in response to a command from the host-to-host control circuit, the second host switches to host role from device role, and the host-to-host control circuit controls whether data is transmitted between the first host and the second host via a DMA path. If the host-to-host control circuit identifies that the second host is an Android smartphone, the host-to-host control circuit determines that data is transmitted between the first host and the second host in a pass-through mode.Type: GrantFiled: May 5, 2020Date of Patent: January 4, 2022Assignee: PROLIFIC TECHNOLOGY INC.Inventors: Tien-Wei Yu, Cheng-Sheng Chan, Chiun-Shiu Chen
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Publication number: 20210407861Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Yuh-Ta FAN, Tien-Wei YU
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Publication number: 20210391220Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Tien-Wei YU
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Publication number: 20210376104Abstract: A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
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Publication number: 20210366778Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
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Patent number: 11183431Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: GrantFiled: September 5, 2019Date of Patent: November 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
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Publication number: 20210305411Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
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Publication number: 20210272955Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.Type: ApplicationFiled: July 21, 2020Publication date: September 2, 2021Inventors: Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Tien-Wei YU, Chia-Ming TSAI
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Patent number: 11088029Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.Type: GrantFiled: April 5, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
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Patent number: 11081584Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.Type: GrantFiled: August 5, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chandrashekhar Prakash Savant, Kin Shun Chong, Tien-Wei Yu, Chia-Ming Tsai, Ming-Te Chen
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Publication number: 20210134974Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventors: Shahaji B. More, Chandrashekhar Prakash Savant, Tien-Wei Yu, Chia-Ming Tsai
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Publication number: 20210074593Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming TSAI, Ming-Te CHEN, Tien-Wei YU
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Publication number: 20210019274Abstract: A USB bridge including a first USB port, a second USB port, a microcontroller, and a host-to-host function circuit is provided. The first USB port is coupled to the first USB host. The second USB port is coupled to the second USB host. The microcontroller is coupled to the first and the second USB ports. The microcontroller communicates with the first and the second USB hosts via the first and the second USB ports, such that the first and the second USB hosts respectively simulate the USB ports of the first and the second USB hosts as virtual COM ports. The host-to-host function circuit is coupled to the microcontroller and configured to perform a host-to-host transmission function by simulating the USB ports as virtual COM ports.Type: ApplicationFiled: September 30, 2020Publication date: January 21, 2021Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chiun-Shiu CHEN
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Publication number: 20210020756Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei WANG, Chia-Ming TSAI, Ke-Chih LIU, Chandrashekhar Prakash SAVANT, Tien-Wei YU
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Publication number: 20200356508Abstract: A host-to-host chip includes: first and second ports coupled to first and second hosts respectively; and a host-to-host control circuit coupled to the first port and the second port. When the host-to-host chip is coupled to the second host, the host-to-host control circuit identifies whether the second host is an i-Phone or an Android smartphone. If the host-to-host control circuit identifies that the second host is an i-Phone smartphone, in response to a command from the host-to-host control circuit, the second host switches to host role from device role, and the host-to-host control circuit controls whether data is transmitted between the first host and the second host via a DMA path. If the host-to-host control circuit identifies that the second host is an Android smartphone, the host-to-host control circuit determines that data is transmitted between the first host and the second host in a pass-through mode.Type: ApplicationFiled: May 5, 2020Publication date: November 12, 2020Applicant: PROLIFIC TECHNOLOGY INC.Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chiun-Shiu CHEN
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Patent number: 10797151Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.Type: GrantFiled: June 11, 2019Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
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Publication number: 20200218681Abstract: The present invention provides a method for automatically identifying host operating system. By applying the method of automatically identifying host operating system in a USB control unit of a USB device by a form of application program, library, variables, and/or operands, the USB control unit is therefore provided with a host operating system identifying function. As such, in case of a specific OS of a host device applying a USB enumeration to the forgoing USB device, the central processing unit would automatically identify (or detect) what the specific OS is. For example, the specific OS is identified as an Apple iOS operating system, a Microsoft Windows operating system, an Apple Mac OS operating system, or a Google Android operating system.Type: ApplicationFiled: March 20, 2020Publication date: July 9, 2020Inventors: TIEN-WEI YU, CHUN-SHIU CHEN
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Publication number: 20200135915Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.Type: ApplicationFiled: August 5, 2019Publication date: April 30, 2020Inventors: Chandrashekhar Prakash SAVANT, Kin Shun CHONG, Tien-Wei YU, Chia-Ming TSAI, Ming-Te CHEN
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Publication number: 20200105894Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.Type: ApplicationFiled: June 11, 2019Publication date: April 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei WANG, Chia-Ming TSAI, Ke-Chih LIU, Chandrashekhar Prakash SAVANT, Tien-Wei YU