Patents by Inventor Tien-Wei YU

Tien-Wei YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098640
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Application
    Filed: April 5, 2019
    Publication date: March 26, 2020
    Applicant: Taiwan Semiconductorr Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Patent number: 10372652
    Abstract: A USB hub includes an upstream port; a first USB device control unit for performing packet format conversion; an FIFO circuit for storing data outputted from the first host; a second USB device control unit for performing packet format conversion; and a plurality of downstream ports. When any one of the downstream ports is coupled to the mobile device, if the first host commands the mobile device to switch to a host role from a device role, the mobile device temporarily disconnects from the USB hub, and the first host commands the USB hub to change an internal routing path. After the mobile device switches to the host role, the first host still performs the host role, and the first USB device control unit performs the device role; the mobile device performs the host role, and the second USB device control unit performs the device role.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 6, 2019
    Assignee: PROLIFIC TECHNOLOGY INC.
    Inventors: Tien-Wei Yu, Cheng-Sheng Chan, Chun-Hsu Chen, Ren-Jie Duan
  • Publication number: 20190236045
    Abstract: A USB bridge including a first USB port, a second USB port, a microcontroller, and a host-to-host function circuit is provided. The first USB port is coupled to the first USB host. The second USB port is coupled to the second USB host. The microcontroller is coupled to the first and the second USB ports. The microcontroller communicates with the first and the second USB hosts via the first and the second USB ports, such that the first and the second USB hosts respectively simulate the USB ports of the first and the second USB hosts as virtual comports. The host-to-host function circuit is coupled to the microcontroller and configured to perform a host-to-host transmission function by simulating the USB ports as virtual comports.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 1, 2019
    Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chiun-Shiu CHEN
  • Publication number: 20190087375
    Abstract: A USB hub includes an upstream port; a first USB device control unit for performing packet format conversion; an FIFO circuit for storing data outputted from the first host; a second USB device control unit for performing packet format conversion; and a plurality of downstream ports. When any one of the downstream ports is coupled to the mobile device, if the first host commands the mobile device to switch to a host role from a device role, the mobile device temporarily disconnects from the USB hub, and the first host commands the USB hub to change an internal routing path. After the mobile device switches to the host role, the first host still performs the host role, and the first USB device control unit performs the device role; the mobile device performs the host role, and the second USB device control unit performs the device role.
    Type: Application
    Filed: June 7, 2018
    Publication date: March 21, 2019
    Applicant: PROLIFIC TECHNOLOGY INC.
    Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chun-Hsu CHEN, Ren-Jie DUAN
  • Publication number: 20180060260
    Abstract: The present invention provides a method and a device capable of automatically identifying host operating system. For the conventionally-used USB devices or USB bridge interfaces cannot effectively identify all kinds of Operation Systems (OS) from an electronic device, the present invention proposes a novel USB device consisting of: a USB physical interface, a central processing unit, and at least one peripheral interface controller; wherein the central processing unit is particularly embedded with an OS identifying library. Moreover, the present invention simultaneously proposes an automatic OS identifying method, which particularly consists of a plurality of OS identifying steps designed based on conventional USB enumeration procedures. Thus, when a specific OS of a host device treats this novel USB device with a USB enumeration, the OS identifying library is able to detect the kind of the specific OS installed in the host device, according to the plurality of OS identifying steps.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Inventors: TIEN-WEI YU, CHUN-SHIU CHEN
  • Patent number: 9263579
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: February 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • Patent number: 9214551
    Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: December 15, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Hua Chang, Tien-Wei Yu, I-Cheng Hu, Chieh-Lung Wu, Yu-Shu Lin, Chun-Jen Chen, Tsung-Mu Yang, Tien-Chen Chan, Chin-Cheng Chien
  • Publication number: 20150263170
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Application
    Filed: May 27, 2015
    Publication date: September 17, 2015
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • Publication number: 20150236158
    Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Ming-Hua Chang, Tien-Wei Yu, I-Cheng Hu, Chieh-Lung Wu, Yu-Shu Lin, Chun-Jen Chen, Tsung-Mu Yang, Tien-Chen Chan, Chin-Cheng Chien
  • Patent number: 9076652
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: July 7, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • Publication number: 20150170916
    Abstract: A semiconductor process includes the steps of providing a substrate with fin structures formed thereon, performing an epitaxy process to grow an epitaxial structure on each fin structure, forming a conformal cap layer on each epitaxial structure, where adjacent conformal cap layers contact each other, and performing an etching process to separate contacting conformal cap layers.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 18, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Wei Yu, Chun-Jen Chen, Tsung-Mu Yang, Ming-Hua Chang, Yu-Shu Lin, Chin-Cheng Chien
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Publication number: 20140349467
    Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.
    Type: Application
    Filed: May 27, 2013
    Publication date: November 27, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Chang, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Yu-Shu Lin, Szu-Hao Lai
  • Patent number: 8853060
    Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Szu-Hao Lai, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Ming-Hua Chang, Yu-Shu Lin, Tsai-Yu Wen, Hsin-Kuo Hsu
  • Publication number: 20140295629
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 2, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Patent number: 8710632
    Abstract: A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tien-Wei Yu, Chin-Cheng Chien, I-Ming Lai, Shin-Chi Chen, Chih-Yueh Li, Fong-Lung Chuang, Chin-I Liao, Kuan-Yu Lin
  • Publication number: 20140070377
    Abstract: A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tien-Wei YU, Chin-Cheng CHIEN, I-Ming LAI, Shin-Chi CHEN, Chih-Yueh LI, Fong-Lung CHUANG, Chin-I LIAO, Kuan-Yu LIN