Patents by Inventor Timo O. Aila

Timo O. Aila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8996846
    Abstract: A system, method, and computer program product are provided for efficiently performing a scan operation. In use, an array of elements is traversed by utilizing a parallel processor architecture. Such parallel processor architecture includes a plurality of processors each capable of physically executing a predetermined number of threads in parallel. For efficiency purposes, the predetermined number of threads of at least one of the processors may be executed to perform a scan operation involving a number of the elements that is a function (e.g. multiple, etc.) of the predetermined number of threads.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 31, 2015
    Assignee: NVIDIA Corporation
    Inventors: Samuli M. Laine, Timo O. Aila, Mark J. Harris
  • Patent number: 8773422
    Abstract: A system, method, and computer program product are provided for grouping linearly ordered primitives. In operation, a plurality of primitives are linearly ordered. Additionally, the primitives are grouped. Furthermore, at least one intersection query is performed, utilizing the grouping.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: July 8, 2014
    Assignee: NVIDIA Corporation
    Inventors: Michael J. Garland, Timo O. Aila, Shubhabrata Sengupta
  • Patent number: 8661226
    Abstract: A system, method, and computer program product are provided for performing a scan operation on a sequence of single-bit values using a parallel processing architecture. In operation, a scan operation instruction is received. Additionally, in response to the scan operation instruction, a scan operation is performed on a sequence of single-bit values using a parallel processor architecture with a plurality of processing elements.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: February 25, 2014
    Assignee: NVIDIA Corporation
    Inventors: Michael J. Garland, Samuli M. Laine, Timo O. Aila, David Patrick Luebke
  • Patent number: 8289324
    Abstract: A system, method, and computer program product are provided for spatial hierarchy traversal. In operation, a spatial hierarchy is traversed for ray tracing. Additionally, a number of nodes traversed in each of a plurality of levels of the spatial hierarchy is stored.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: October 16, 2012
    Assignee: NVIDIA Corporation
    Inventors: Samuli M. Laine, Timo O. Aila, David Patrick Luebke
  • Patent number: 8072454
    Abstract: A system, method, and computer program product are provided for selecting a ray tracing entity from a group of ray tracing entities for processing by a parallel processing architecture. In operation, it is determined whether at least one thread in a parallel processing architecture has completed processing a ray tracing entity. Further, an additional ray tracing entity is selected from a group of ray tracing entities for processing by the parallel processing architecture, based on the determination.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: December 6, 2011
    Assignee: NVIDIA Corporation
    Inventors: Timo O. Aila, Samuli M. Laine
  • Patent number: 8065288
    Abstract: A system, method, and computer program product are provided for testing a query against multiple sets of objects. In operation, a query is tested against a first set of objects, utilizing a single instruction multiple data processing architecture. Additionally, a second set of objects is selected based on a result of testing the query against the first set of objects. Furthermore, the query is tested against the second set of objects, utilizing the single instruction multiple data processing architecture.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: November 22, 2011
    Assignee: NVIDIA Corporation
    Inventors: Michael J. Garland, Samuli M. Laine, Timo O. Aila
  • Patent number: 8059123
    Abstract: A system, method, and computer program product are provided for postponing the execution of primitive intersection. In operation, at, least one node traversal operation and at least one primitive intersection operation is executed, utilizing a parallel processing architecture. Additionally, the execution of the at least one primitive intersection operation is postponed.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: November 15, 2011
    Assignee: NVIDIA Corporation
    Inventors: Samuli M. Laine, Timo O. Aila
  • Patent number: 7999808
    Abstract: A system, method, and computer program product are provided for executing node traversal or primitive intersection using a parallel processing architecture. In operation, it is determined whether a plurality of threads in a parallel processing architecture are to execute node traversal or primitive intersection. Additionally, the node traversal or the primitive intersection is executed, based on the determination.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: August 16, 2011
    Assignee: NVIDIA Corporation
    Inventors: Timo O. Aila, Samuli M. Laine
  • Publication number: 20090132878
    Abstract: A system, method, and computer program product are provided for performing a scan operation on a sequence of single-bit values using a parallel processing architecture. In operation, a scan operation instruction is received. Additionally, in response to the scan operation instruction, a scan operation is performed on a sequence of single-bit values using a parallel processor architecture with a plurality of processing elements.
    Type: Application
    Filed: November 15, 2007
    Publication date: May 21, 2009
    Inventors: Michael J. Garland, Samuli M. Laine, Timo O. Aila, David Patrick Luebke
  • Publication number: 20090089542
    Abstract: A system, method, and computer program product are provided for efficiently performing a scan operation. In use, an array of elements is traversed by utilizing a parallel processor architecture. Such parallel processor architecture includes a plurality of processors each capable of physically executing a predetermined number of threads in parallel. For efficiency purposes, the predetermined number of threads of at least one of the processors may be executed to perform a scan operation involving a number of the elements that is a function (e.g. multiple, etc.) of the predetermined number of threads.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Samuli M. Laine, Timo O. Aila, Mark J. Harris