Patents by Inventor Timothy Daubenspeck

Timothy Daubenspeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7704804
    Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20090149013
    Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 11, 2009
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20080067676
    Abstract: An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.
    Type: Application
    Filed: November 16, 2007
    Publication date: March 20, 2008
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20080064189
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Publication number: 20080023833
    Abstract: A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer includes a hole and a trench, wherein the hole is directly above the electrically conductive bond pad, and wherein the trench is not filled by any electrically conductive material; and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad.
    Type: Application
    Filed: October 10, 2007
    Publication date: January 31, 2008
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20070252274
    Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 1, 2007
    Inventors: Timothy Daubenspeck, Mukta Farooq, Jeffrey Gambino, Christopher Muzzy, Kevin Petrarca, Wolfgang Sauter
  • Publication number: 20070212872
    Abstract: By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be provided.
    Type: Application
    Filed: May 14, 2007
    Publication date: September 13, 2007
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Kevin Ostrowski, Wolfgang Sauter
  • Publication number: 20070200229
    Abstract: A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
    Type: Application
    Filed: February 27, 2006
    Publication date: August 30, 2007
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter, David Questad
  • Publication number: 20070176288
    Abstract: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 2, 2007
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20070111502
    Abstract: A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.
    Type: Application
    Filed: January 5, 2007
    Publication date: May 17, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20070105359
    Abstract: An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 10, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20070080455
    Abstract: A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 12, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donna Zupanski-Nielsen, William Landers, Ian Melville, Roger Quon, Timothy Daubenspeck, Kamalesh Srivastava, Mary Cullinan-Scholl, Lawrence Clevenger, Christopher Muzzy
  • Publication number: 20070013071
    Abstract: A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.
    Type: Application
    Filed: June 24, 2005
    Publication date: January 18, 2007
    Applicant: International Business Machines Corporation
    Inventors: James Adkisson, Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20060292830
    Abstract: A semiconductor structure and method for chip dicing. The method includes (a) providing a semiconductor substrate and (b) forming first and second device regions in and at top of the substrate. The first and second device regions are separated by a semiconductor border region of the substrate. The method further includes (c) forming N interconnect layers, in turn, directly above the semiconductor border region and the first and second device regions. N is a positive integer greater than one. Each of the N interconnect layers includes an etchable portion directly above the semiconductor border region. The etchable portions of the N interconnect layers form a continuous etchable block directly above the semiconductor border region. The method further includes (d) removing the continuous etchable block by etching, and (e) cutting with a laser through the semiconductor border region via an empty space of the removed continuous etchable block.
    Type: Application
    Filed: August 9, 2006
    Publication date: December 28, 2006
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20060281197
    Abstract: A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 14, 2006
    Applicant: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter, Jeffrey Zimmerman
  • Publication number: 20060267136
    Abstract: An Integrated Circuit (IC) chip with fused circuits and method of making the IC. Fuses in an upper wiring layer are formed using a multi-tone mask to define rounded bottom corners on the fuses, while wiring in the upper wiring layer maintain a rectangular cross-section.
    Type: Application
    Filed: May 24, 2005
    Publication date: November 30, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20060244139
    Abstract: A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter
  • Publication number: 20060246703
    Abstract: A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter, Edmund Sprogis
  • Publication number: 20060223242
    Abstract: A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The crack stop void is formed simultaneously with the formation of an interconnect structure.
    Type: Application
    Filed: March 24, 2006
    Publication date: October 5, 2006
    Inventors: Timothy Daubenspeck, Christopher Muzzy, Paul McLaughlin, Judith Wright, Jean Wynne, Dae Jung
  • Publication number: 20060197228
    Abstract: By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be provided.
    Type: Application
    Filed: March 4, 2005
    Publication date: September 7, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Kevin Ostrowski, Wolfgang Sauter