Patents by Inventor Timothy Hume Heil

Timothy Hume Heil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11768714
    Abstract: Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: September 26, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xiaoling Xu, Timothy Hume Heil, Deepak Goel
  • Publication number: 20220405151
    Abstract: Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Inventors: Xiaoling XU, Timothy Hume HEIL, Deepak GOEL
  • Publication number: 20220261456
    Abstract: A computing device, including a hardware accelerator configured to receive a first matrix and receive a second matrix. The hardware accelerator may, for a plurality of partial matrix regions, in a first iteration, read a first submatrix of the first matrix and a second submatrix of the second matrix into a front-end processing area. The hardware accelerator may multiply the first submatrix by the second submatrix to compute a first intermediate partial matrix. In each of one or more subsequent iterations, the hardware accelerator may read an additional submatrix into the front end processing area. The hardware accelerator may compute an additional intermediate partial matrix as a product of the additional submatrix and a submatrix reused from an immediately prior iteration. The hardware accelerator may compute each partial matrix as a sum of two or more of the intermediate partial matrices and may output the plurality of partial matrices.
    Type: Application
    Filed: January 14, 2021
    Publication date: August 18, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Derek Edward Davout GLADDING, Nitin Naresh GAREGRAT, Timothy Hume HEIL, Balamurugan KULANTHIVELU VELUCHAMY
  • Patent number: 11176448
    Abstract: An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 16, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chad Balling McBride, Timothy Hume Heil, Amol Ashok Ambardekar, George Petre, Kent D. Cedola, Larry Marvin Wall, Boris Bobrov
  • Patent number: 10862509
    Abstract: Techniques are described for encoding symbols using a new algorithm that provides a flexible Huffman tree approximation and that can be used for low latency encoding. For example, the new algorithm can perform encoding using one or more of the following phases: Shannon-based binning, code space optimization, tree completion, and code assignment.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 8, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Timothy Hume Heil, Bogdan Alexandru Burlacu
  • Publication number: 20200233820
    Abstract: An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Inventors: Chad Balling McBRIDE, Timothy Hume HEIL, Amol Ashok AMBARDEKAR, George PETRE, Kent D. CEDOLA, Larry Marvin WALL, Boris BOBROV
  • Patent number: 10628345
    Abstract: An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: April 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chad Balling McBride, Timothy Hume Heil, Amol Ashok Ambardekar, George Petre, Kent D. Cedola, Larry Marvin Wall, Boris Bobrov
  • Publication number: 20180299943
    Abstract: An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventors: Chad Balling McBRIDE, Timothy Hume HEIL, Amol Ashok AMBARDEKAR, George PETRE, Kent D. CEDOLA, Larry Marvin WALL, Boris BOBROV
  • Patent number: 8635180
    Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
    Type: Grant
    Filed: February 6, 2011
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Giora Biran, Christoph Hagleitner, Timothy Hume Heil, Jan Van Lunteren
  • Patent number: 8495334
    Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
    Type: Grant
    Filed: February 6, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Giora Biran, Christoph Hagleitner, Timothy Hume Heil, Jan Van Lunteren
  • Patent number: 8255887
    Abstract: A memory management mechanism requires data structures to be explicitly deallocated in the programming code, but deallocation does not immediately make the memory available for reuse. Before a deallocated memory region can be reused, memory is scanned for pointers to the deallocated region, and any such pointer is set to null. The deallocated memory is then available for reuse. Preferably, deallocated memory regions are accumulated, and an asynchronous memory cleaning process periodically scans memory to nullify the pointers. In order to prevent previously scanned memory becoming contaminated with a dangling pointer before the scan is finished, any write to a pointer is checked to verify that the applicable target address has not been deallocated.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventor: Timothy Hume Heil
  • Publication number: 20120204000
    Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
    Type: Application
    Filed: February 6, 2011
    Publication date: August 9, 2012
    Applicant: International Business Machines Corporation
    Inventors: Giora Biran, Christoph Hagleitner, Timothy Hume Heil, Jan Van Lunteren
  • Publication number: 20120203729
    Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
    Type: Application
    Filed: February 6, 2011
    Publication date: August 9, 2012
    Applicant: International Business Machines Corporation
    Inventors: Giora Biran, Christoph Hagleitner, Timothy Hume Heil, Jan Van Lunteren
  • Publication number: 20120124291
    Abstract: A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: International Business Machines Corporation
    Inventors: Heather D. Achilles, Timothy Hume Heil, Anil Krishna, Nicholas David Lindberg, Steven Paul VanderWiel, Shaul Yifrach
  • Patent number: 8140833
    Abstract: A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured to provide improved performance based upon the current workload.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Powers Bradford, Richard James Eickemeyer, Timothy Hume Heil, Harold F. Kossman, Timothy John Mullins
  • Patent number: 8078852
    Abstract: An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: December 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Muawya Mohamed Al-Otoom, Timothy Hume Heil, Anil Krishna, Ken Van Vu
  • Patent number: 8028118
    Abstract: Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: September 27, 2011
    Assignee: Internation Business Machines Corporation
    Inventors: Timothy Hume Heil, James Allen Rose, Andrew Henry Wottreng
  • Patent number: 7826399
    Abstract: A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy Hume Heil, Michael Steven Siegel, Jeffrey R. Summers, Steven Paul VanderWiel
  • Patent number: 7760669
    Abstract: In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy Hume Heil, Michael Steven Siegel, Jeffrey R. Summers, Steven Paul VanderWiel
  • Patent number: 7739477
    Abstract: Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Powers Bradford, Jason Nathaniel Dale, Kimberly Marie Fernsler, Timothy Hume Heil, James Allen Rose