Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

Abstract: A memory system includes multiple levels of cache and an auxiliary storage element for storing a copy of a cache line from one of the levels of cache when the cache line of the one of the levels of cache is determined to have been modified. The system also includes a flag configured to indicate a cache state of the modified cache line. The cache state indicates the modified cache line has been copied to the auxiliary storage element. The system also includes a controller communicatively coupled to each of the multiple levels of cache and the auxiliary storage element. The controller is configured to, in response to determining the cache line of the one of the levels of cache has been modified, copy the modified cache line to the auxiliary storage element and set the flag for the modified cache line to indicate the cache state.

Abstract: In one aspect a method includes determining, by a controller of a memory system, that a cache line of one of a plurality of levels of cache in the memory system has been modified. An aspect also includes copying the modified cache line to an auxiliary storage element, and setting a flag in a cache directory for the modified cache line to indicate a cache state of mirrored modified.

Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key from the computer system is also received by the memory module. A reference key is retrieved by the memory module, the reference key is stored on the memory module. A comparison status is generated by the memory module by comparing the verification key with the reference key. A response is sent to the computer by the memory module that is dependent upon the comparison status.

Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.

Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.

Abstract: A memory module secures data stored on the memory module. A request for the data from a computer system is received by the memory module. A verification key from the computer system is also received by the memory module. A reference key is retrieved by the memory module, the reference key is stored on the memory module. A comparison status is generated by the memory module by comparing the verification key with the reference key. A response is sent to the computer by the memory module that is dependent upon the comparison status.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.