Patents by Inventor Timothy J. McArdle

Timothy J. McArdle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10756184
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Timothy J. McArdle, Judson R. Holt, Steffen A. Sichler, Ömür I. Aydin, Wei Hong, Yi Qi, Hui Zang, Liu Jiang
  • Patent number: 10741556
    Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Lakshmanan H. Vanamurthy, Scott Beasor, Timothy J. McArdle, Judson R. Holt, Hao Zhang
  • Patent number: 10680065
    Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 9, 2020
    Inventors: George R. Mulfinger, Timothy J. McArdle, Jody Fronheiser, El Mehdi Bazizi, Yi Qi
  • Publication number: 20200144365
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 7, 2020
    Inventors: George R. MULFINGER, Timothy J. MCARDLE, Judson R. HOLT, Steffen A. SICHLER, Ömür I. AYDIN, Wei HONG, Yi QI, Hui ZANG, Liu JIANG
  • Publication number: 20200044029
    Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: George R. Mulfinger, Timothy J. McArdle, Jody Fronheiser, El Mehdi Bazizi, Yi Qi
  • Patent number: 10396078
    Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
  • Patent number: 10388654
    Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Judson R. Holt, George Mulfinger, Timothy J. McArdle, Thomas Merbeth, Ömür Aydin, Ruilong Xie
  • Publication number: 20190214387
    Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Judson R. Holt, George Mulfinger, Timothy J. McArdle, Thomas Merbeth, Ömür Aydin, Ruilong Xie
  • Patent number: 10326007
    Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Timothy J. McArdle, Judson Robert Holt
  • Patent number: 10236343
    Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dina H. Triyoso, Timothy J. McArdle, Judson R. Holt, Amy L. Child, George R. Mulfinger
  • Patent number: 10204984
    Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Matthew W. Stoker, Judson R. Holt, Timothy J. McArdle, Annie Lévesque
  • Publication number: 20190043967
    Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: February 7, 2019
    Inventors: George Robert MULFINGER, Ryan SPORER, Timothy J. MCARDLE, Judson Robert HOLT
  • Publication number: 20190043944
    Abstract: At least one method, apparatus and system disclosed herein involves forming increased surface regions within EPI structures. A fin on a semiconductor substrate is formed. On a top portion of the fin, an epitaxial (EPI) structure is formed. The EPI structure has a first EPI portion having a first material and a second EPI portion having a second material. The first and second EPI portions are separated by a first separation layer. A first cavity is formed within the EPI structure by removing a portion of the second material in the second portion. A first conductive material is deposited into the first cavity.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 7, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Matthew W. Stoker, Judson R. Holt, Timothy J. McArdle, Annie Lévesque
  • Publication number: 20190027370
    Abstract: Methods of forming a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a cavity extending through the semiconductor fin and into a substrate fin underlying the semiconductor fin. After the cavity is formed, the semiconductor fin is etched selective to the substrate fin with a second etching process to widen a portion of the cavity.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: George R. Mulfinger, Hyun-Jin Cho, Anil Kumar, Timothy J. McArdle
  • Patent number: 10134876
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bharat V. Krishnan, Timothy J. McArdle, Rinus Tek Po Lee, Shishir K. Ray, Akshey Sehgal
  • Publication number: 20180286982
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Bharat V. KRISHNAN, Timothy J. MCARDLE, Rinus Tek Po LEE, Shishir K. Ray, Akshey SEHGAL
  • Publication number: 20180286863
    Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
  • Publication number: 20180233505
    Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.
    Type: Application
    Filed: September 28, 2017
    Publication date: August 16, 2018
    Inventors: George R. MULFINGER, Lakshmanan H. VANAMURTHY, Scott BEASOR, Timothy J. MCARDLE, Judson R. HOLT, Hao ZHANG
  • Patent number: 10043893
    Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins formed over a substrate; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a u-shaped cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each u-shaped cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Timothy J. McArdle, Judson Robert Holt
  • Patent number: 10020307
    Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang