Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.

Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.

Abstract: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: A media processing system with an improved method and device for rotating a video image is provided. Embodiments of the media processing system include a video decoder with the ability to output decoded video in a landscape or portrait orientation. In some embodiments, the video output orientation is based on the physical orientation of the display as indicated by an electronic sensor.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

Abstract: In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

Abstract: Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.

Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.