Patents by Inventor Timothy J. Williams
Timothy J. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11309966Abstract: A method and apparatus for latency control in an optical network. A management node such as an OLT in a PON sends a discovery message intending to prompt joining network nodes such as ONUs to send a response on a first wavelength during a quiet window established for this purpose. When a response is received, a secondary upstream-transmission wavelength is assigned to the ONU. When the ONU sends data upstream according to a schedule calculated by the ONT, which schedule may include transmission times using the assigned secondary wavelength. In this case, the assigned secondary wavelength will be scheduled using a relatively smaller or no quiet window. This scheduling may be determined in part by the service or services used by the ONU.Type: GrantFiled: August 3, 2020Date of Patent: April 19, 2022Assignee: NOKIA OF AMERICA CORPORATIONInventors: William B. Weeber, Timothy J. Williams
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Publication number: 20210075512Abstract: A method and apparatus for latency control in an optical network. A management node such as an OLT in a PON sends a discovery message intending to prompt joining network nodes such as ONUs to send a response on a first wavelength during a quiet window established for this purpose. When a response is received, a secondary upstream-transmission wavelength is assigned to the ONU. When the ONU sends data upstream according to a schedule calculated by the ONT, which schedule may include transmission times using the assigned secondary wavelength. In this case, the assigned secondary wavelength will be scheduled using a relatively smaller or no quiet window. This scheduling may be determined in part by the service or services used by the ONU.Type: ApplicationFiled: August 3, 2020Publication date: March 11, 2021Inventors: William B. Weeber, Timothy J. Williams
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Patent number: 10735098Abstract: A method and apparatus for latency control in an optical network. A management node such as an OLT in a PON sends a discovery message intending to prompt joining network nodes such as ONUs to send a response on a first wavelength during a quiet window established for this purpose. When a response is received, a secondary upstream-transmission wavelength is assigned to the ONU. When the ONU sends data upstream according to a schedule calculated by the ONT, which schedule may include transmission times using the assigned secondary wavelength. In this case, the assigned secondary wavelength will be scheduled using a relatively smaller or no quiet window. This scheduling may be determined in part by the service or services used by the ONU.Type: GrantFiled: November 20, 2017Date of Patent: August 4, 2020Assignee: NOKIA OF AMERICA CORPORATIONInventors: William B. Weeber, Timothy J. Williams
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Publication number: 20180145757Abstract: A method and apparatus for latency control in an optical network. A management node such as an OLT in a PON sends a discovery message intending to prompt joining network nodes such as ONUs to send a response on a first wavelength during a quiet window established for this purpose. When a response is received, a secondary upstream-transmission wavelength is assigned to the ONU. When the ONU sends data upstream according to a schedule calculated by the ONT, which schedule may include transmission times using the assigned secondary wavelength. In this case, the assigned secondary wavelength will be scheduled using a relatively smaller or no quiet window. This scheduling may be determined in part by the service or services used by the ONU.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Applicant: Alcatel-Lucent USA Inc.Inventors: William B. Weeber, Timothy J. Williams
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Patent number: 9848740Abstract: A storage system for a shower enclosure includes a first wall member, a second wall member, and a storage accessory. The first wall member includes a corner defining a recessed portion. The first wall member further includes a corner notch disposed along the corner within the recessed portion, and a first side notch disposed along an inner side surface of the first wall member adjacent the recessed portion. The second wall member is coupled to the first wall member at an end of the corner adjacent the recessed portion and is oriented perpendicular to the first wall member. The second wall member includes a second side notch disposed along an inner side surface of the second wall member. The storage accessory is removably coupled between the first wall member and the second wall member at the corner notch, the first side notch, and the second side notch.Type: GrantFiled: December 15, 2015Date of Patent: December 26, 2017Assignee: KOHLER CO.Inventors: Alan T. McDonald, Sarah K. O'Brien, Luke B. Zimbric, Timothy J. Williams, Kyle A. Marten, Gurusiddeshwar Gudimani
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Patent number: 9720865Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.Type: GrantFiled: November 13, 2014Date of Patent: August 1, 2017Assignee: Cypress Semiconductor CorporationInventors: Timothy J. Williams, David G. Wright, Harold Kutz, Eashwar Thiagarajan, Warren S. Snyder, Mark E Hastings
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Publication number: 20160166119Abstract: A storage system for a shower enclosure includes a first wall member, a second wall member, and a storage accessory. The first wall member includes a corner defining a recessed portion. The first wall member further includes a corner notch disposed along the corner within the recessed portion, and a first side notch disposed along an inner side surface of the first wall member adjacent the recessed portion. The second wall member is coupled to the first wall member at an end of the corner adjacent the recessed portion and is oriented perpendicular to the first wall member. The second wall member includes a second side notch disposed along an inner side surface of the second wall member. The storage accessory is removably coupled between the first wall member and the second wall member at the corner notch, the first side notch, and the second side notch.Type: ApplicationFiled: December 15, 2015Publication date: June 16, 2016Inventors: Alan T. McDonald, Sarah K. O'Brien, Luke B. Zimbric, Timothy J. Williams, Kyle A. Marten, Gurusiddeshwar Gudimani
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Patent number: 9143134Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.Type: GrantFiled: June 12, 2013Date of Patent: September 22, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Harold M. Kutz, Timothy J. Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Kohagen, David G. Wright, Mark E. Hastings, Dennis Raymond Seguine
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Patent number: 9098641Abstract: A configurable bus includes a plurality of bus segments. The configurable bus also includes two or more pluralities of input/output (I/O) ports. Each bus segment is coupled to at least one of the pluralities of I/O ports. Also coupled to the bus segments is a cross-couple unit that is configurable to selectively couple any of the bus segments together.Type: GrantFiled: January 25, 2007Date of Patent: August 4, 2015Assignee: Cypress Semiconductor CorporationInventors: Harold Kutz, Warren S. Snyder, Timothy J. Williams, Eashwar Thiagarajan
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Patent number: 8890600Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.Type: GrantFiled: May 13, 2013Date of Patent: November 18, 2014Assignee: Cypress Semicondductor CorporationInventors: Timothy J. Williams, Harold Kutz, David G. Wright, Eashwar Thiagarajan, Warren S. Snyder, Mark E. Hastings
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Publication number: 20130336081Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.Type: ApplicationFiled: June 11, 2013Publication date: December 19, 2013Inventors: Michael Sheets, Timothy J. Williams
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Patent number: 8564252Abstract: A circuit for charging a capacitive load to a reference voltage in a capacitive sensor measurement circuit includes a reference buffer, a boost buffer, and drive logic. The reference buffer and the boost buffer are coupled with the capacitive load to be charged. The boost buffer first charges the capacitive load towards the reference voltage at a first rate of charging, and then ceases charging. The reference buffer subsequently continues charging at a slower second rate to settle the voltage across the capacitive load to within a tolerable range of the reference voltage.Type: GrantFiled: November 9, 2007Date of Patent: October 22, 2013Assignee: Cypress Semiconductor CorporationInventors: Nandakishore Raimar, Timothy J. Williams
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Patent number: 8558578Abstract: A programmable input/output circuit includes a programmable output circuit configured to drive an output signal to an input/output pad at a plurality of voltages, at least one of the plurality of voltages being supplied by an external circuit. The programmable input/output circuit further includes a programmable input configured to detect an input signal from the input/output pad at the plurality of voltages. The voltage levels of the input and output circuits may be independently and dynamically controllable.Type: GrantFiled: March 22, 2012Date of Patent: October 15, 2013Assignee: Cypress Semiconductor CorporationInventors: Timothy J. Williams, David G. Wright, Gregory J. Verge, Bruce E. Byrkett
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Patent number: 8290368Abstract: A system, and methods for detecting collisions on multipoint shared optical media, comprising an optical receiver, clock phase detector, clock recovery circuit, and a Passive Optical Network (PON) that transmits optical signals wherein the PON, the clock recovery circuit, and the clock phase detector are communicably coupled to the optical receiver, detecting of the collision is determined by a distortion of transition times of the optical signals at the optical receiver.Type: GrantFiled: July 9, 2009Date of Patent: October 16, 2012Assignee: Alcatel LucentInventor: Timothy J Williams
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Patent number: 8179161Abstract: A programmable input/output circuit includes a programmable output circuit configured to drive an output signal to an input/output pad at a plurality of voltages. The programmable input/output circuit further includes a programmable input configured to detect an input signal from the input/output pad at a plurality of voltages. The voltage levels of the input and output circuits may be independently and dynamically controllable.Type: GrantFiled: April 2, 2010Date of Patent: May 15, 2012Assignee: Cypress Semiconductor CorporationInventors: Timothy J. Williams, David G. Wright, Gregory J. Verge, Bruce E. Byrkett
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Patent number: 8089384Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.Type: GrantFiled: April 5, 2010Date of Patent: January 3, 2012Assignee: Cypress Semiconductor CorporationInventors: Timothy J. Williams, James H. Shutt, Warren Snyder, Dennis Seguine
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Patent number: 8089383Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.Type: GrantFiled: March 26, 2010Date of Patent: January 3, 2012Assignee: Cypress Semiconductor CorporationInventors: Timothy J. Williams, James H. Shutt, Warren Snyder, Dennis Seguine
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Patent number: 8049569Abstract: A clock generation circuit is provided for improving the accuracy of a low power oscillator circuit contained therein. The clock generation circuit includes a crystal-less oscillator having at least two distinct frequency modes, including a low frequency mode and a high frequency mode. In some cases, the crystal-less oscillator may be adapted to generate a first clock frequency with relatively high accuracy and a second clock frequency with relatively low accuracy. A calibration and control circuit is included within the clock generation circuit for increasing the accuracy of the second clock frequency. In particular, the calibration and control circuit increases accuracy by using the first clock frequency to calibrate the second clock frequency generated by the same crystal-less oscillator. A system comprising the clock generation circuit and methods for operating a crystal-less oscillator having at least two distinct frequency modes are also provided herein.Type: GrantFiled: September 5, 2007Date of Patent: November 1, 2011Assignee: Cypress Semiconductor CorporationInventors: David G. Wright, Timothy J. Williams
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Publication number: 20110008045Abstract: A system, and methods for detecting collisions on multipoint shared optical media, comprising an optical receiver, clock phase detector, clock recovery circuit, and a Passive Optical Network (PON) that transmits optical signals wherein the PON, the clock recovery circuit, and the clock phase detector are communicably coupled to the optical receiver, detecting of the collision is determined by a distortion of transition times of the optical signals at the optical receiver.Type: ApplicationFiled: July 9, 2009Publication date: January 13, 2011Applicant: ALCATEL-LUCENT USA, INC.Inventor: Timothy J. Williams
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Publication number: 20100283647Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.Type: ApplicationFiled: March 26, 2010Publication date: November 11, 2010Inventors: Timothy J. Williams, James H. Shutt, Warren Snyder, Dennis Seguine