Patents by Inventor Timothy M. Hollis

Timothy M. Hollis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942404
    Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Scott R. Cyr, Stephen F. Moxham, Matthew A. Prather, Scott Smith
  • Publication number: 20240063188
    Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Publication number: 20240045620
    Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11894099
    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyun Yoo Lee, Timothy M. Hollis, Dong Soon Lim
  • Publication number: 20240022457
    Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 18, 2024
    Inventor: Timothy M. Hollis
  • Publication number: 20240004814
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Application
    Filed: September 18, 2023
    Publication date: January 4, 2024
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11862294
    Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11860731
    Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: January 2, 2024
    Inventors: Martin Brox, Peter Mayer, Wolfgang Anton Spirkl, Thomas Hein, Michael Dieter Richter, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11837580
    Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11804992
    Abstract: Systems and methods for implementation of modified decision feedback equalization. In one embodiment, a method, includes sweeping a reference voltage signal across a set of voltages to find a center point of an eye diagram, determining whether an asymmetry is present in the eye diagram relative to the center point of the eye diagram, and when an asymmetry is determined to be present, generating a control signal to select a mode of decision feedback equalization to be applied to an input data bit.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: October 31, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 11797229
    Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 24, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11789890
    Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: October 17, 2023
    Inventors: Thomas H. Kinsley, George E. Pax, Timothy M. Hollis, Yogesh Sharma, Randon K. Richards, Chan H. Yoo, Gregory A. King, Eric J. Stave
  • Patent number: 11775460
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: October 3, 2023
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11777767
    Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: October 3, 2023
    Inventor: Timothy M. Hollis
  • Publication number: 20230275016
    Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: David K. Ovard, Thomas Hein, Timothy M. Hollis, Walter L. Moden
  • Patent number: 11699477
    Abstract: A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 11675728
    Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11670578
    Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David K. Ovard, Thomas Hein, Timothy M. Hollis, Walter L. Moden
  • Publication number: 20230120654
    Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Timothy M. Hollis, James S. Rehmeyer, Baekkyu Choi, Yogesh Sharma, Eric J. Stave, Brian W. Huber, Miles S. Wiscombe
  • Publication number: 20230116891
    Abstract: A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Timothy M. Hollis