Abstract: Generally, and in one form of the invention, a method is disclosed for reducing base-to-emitter leakage in a bipolar transistor having an active region 22 bounded by an isolation implant boundary 24, said method comprising arranging an emitter contact 26 and a base contact 36 such that at a crossing of the contacts over the implant boundary, a leakage current between the contacts along the boundary is limited by a necessity to transit the thickness of a layer of material, and whereby said transistor exhibits improved gain, noise performance, and reliability.

Abstract: The invention described herein includes, in one of its forms, a method for fabricating a bipolar transistor having a reduced base-collector capacitance. A specific embodiment includes forming a selectively etchable material 44 over a highly doped subcollector layer 42, removing portions of the selectively etchable material 44 and then growing collector 46, base 48, and emitter 50 layers over the structure. The selectively etchable material 44 may then be removed to form an undercut region between the highly doped subcollector layer 42 and the highly doped base 48. The structure provides the advantage of improved high-frequency and high-power operation.

Abstract: A method of fabricating a heterojunction bipolar transistor and the transistor by providing a substrate of a group III-V semiconductor material, doping a first selected region at a surface of the substrate a predetermined first conductivity type, concurrently or separately incorporating a group III element into a portion of the first selected region, doping the portion of the first selected region to a second conductivity type with a laser beam to cause melting and subsequent recrystallization of said substrate and forming contacts to the portion of the first selected region and to the first selected region. The portion of the first selected region extends farther into the substrate than the remainder of the first selected region. A complementary transistor can be concurrently fabricated using the same steps except that p-implants replace the n-implants and n-doped InGaAs instead of p-doped InGaAs forms the base layer.

Abstract: In one form of the invention, a method is disclosed for removing portions of successive layers of GaAs 34 and GaInP 32 comprising the steps of: performing an anisotropic reactive ion etch on the GaAs layer; and performing an isotropic wet etch on the GaInP layer, whereby a mesa formed as a result of the reactive ion etch and the wet etch has substantially vertical sidewalls, and further whereby GaInP/GaAs structures having dimensions of less than approximately 3.0 .mu.m may be fabricated.

Abstract: A strained In.sub.y Ga.sub.l-y As layer is employed in a GaAs/Al.sub.x Ga.sub.l-x As transistor. Since the bandgap of In.sub.y Ga.sub.l-y As is much smaller than that of GaAs, there is no need for a troublesome large-mole-fraction of aluminum in the Al.sub.x Ga.sub.l-x As layer in order to maintain a large bandgap discontinuity. This and other advantages of the structure set forth result in devices having improved operating characteristics.