Patents by Inventor Tin-Fook Ngai

Tin-Fook Ngai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140269322
    Abstract: Embodiments of an enhanced Node B (eNB) configured for use in a cooperative radio access networks (C-RAN) and method for central baseband unit (BBU) processing are generally described herein. In some embodiments, the eNB may include a baseband unit (BBU) processing pool comprising a plurality of processing units. The BBU processing pool is configured to share the processing load of several sectors. A control unit may monitor the processing load of the processing units and perform dynamic load sharing by migrating the baseband processing between the processing units without changing a carrier used by user equipment operating with a sector.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 18, 2014
    Inventors: Guangjie Li, Xuebin Yang, Senjie Zhang, Tin-Fook Ngai
  • Publication number: 20140237303
    Abstract: An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
    Type: Application
    Filed: December 23, 2011
    Publication date: August 21, 2014
    Inventors: Jayashankar Bharadwaj, Victor W. Lee, Kim Daehyun, Nalini Vasudevan, Tin-Fook Ngai, Albert Hartono, Sara S. Baghsorkhi
  • Publication number: 20140223139
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
    Type: Application
    Filed: December 23, 2011
    Publication date: August 7, 2014
    Inventors: Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono, Sara Baghsorkhi, Nalini Vasudevan
  • Publication number: 20140122832
    Abstract: Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Inventors: Tin-Fook Ngai, Chunxiao Lin, Yingzhe Shen, Chao Zhang
  • Publication number: 20140089634
    Abstract: An apparatus, system and method are described for identifying identical elements in a vector register.
    Type: Application
    Filed: December 23, 2011
    Publication date: March 27, 2014
    Inventors: Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono, Sara S. Baghsorkhi, Nalini Vasudevan
  • Publication number: 20130311530
    Abstract: An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N-1 reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals.
    Type: Application
    Filed: March 30, 2012
    Publication date: November 21, 2013
    Inventors: Victor W. Lee, Jayashankar Bharadwaj, Daehyun Kim, Nalini Vasudevan, Tin-Fook Ngai, Albert Hartono, Sara Baghsorkhi
  • Publication number: 20130111194
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: December 20, 2012
    Publication date: May 2, 2013
    Inventors: Ed Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Colins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 8296748
    Abstract: A method to provide effective control and data flow information in an Intermediate Representation (IR) form. A Path Sensitive single Assignment (PSA) IR form with effective and explicit control and data path information supports control flow sensitive optimizations such as path sensitive symbolic substitution, array privatization and speculative multi threading. In the definition of PSA form, besides defining new versioned variables, the gamma functions keep control path information. The gamma function in PSA form keeps the basic attribute of SSA IR form and only one definition exists for each use. Therefore, all existing Single Static Assignment (SSA) IR form based analysis can be applied in PSA form. The gamma function in PSA form keeps all essential control flow information and eliminates unnecessary predicates at the same time.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventors: Buqi Cheng, Tin-Fook Ngai, Zhaohui Du, PeiNan Zhang
  • Publication number: 20110167416
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: December 25, 2010
    Publication date: July 7, 2011
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Patent number: 7770162
    Abstract: A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a shifting vector for the loop from the dependence equations group, wherein the shifting vector to represent an offset to apply to each statement in the loop for statement shifting. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: August 3, 2010
    Assignee: Intel Corporation
    Inventors: Li Liu, Zhaohui Du, Bu Qi Cheng, Shiwei Liao, Gansha Wu, Tin-fook Ngai
  • Publication number: 20100023931
    Abstract: A method to provide effective control and data flow information in an Intermediate Representation (IR) form. A Path Sensitive single Assignment (PSA) IR form with effective and explicit control and data path information supports control flow sensitive optimizations such as path sensitive symbolic substitution, array privatization and speculative multi threading. In the definition of PSA form, besides defining new versioned variables, the gamma functions keep control path information. The gamma function in PSA form keeps the basic attribute of SSA IR form and only one definition exists for each use. Therefore, all existing Single Static Assignment (SSA) IR form based analysis can be applied in PSA form. The gamma function in PSA form keeps all essential control flow information and eliminates unnecessary predicates at the same time.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 28, 2010
    Inventors: Buqi Cheng, Tin-Fook Ngai, Zhaohui Du, PeiNan Zhang
  • Patent number: 7627864
    Abstract: A method to optimize speculative parallel thread execution comprises selecting a plurality of partition candidate pairs for speculative parallel thread execution, transforming each partition candidate pair of the plurality of partition candidate pairs to improve the expected performance gain of each pair, and selecting a set of one or more transformed partition candidate pairs that do not interfere with each other and produce a maximum expected performance gain.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: December 1, 2009
    Assignee: Intel Corporation
    Inventors: Zhao Hui Du, Tin-fook Ngai, Chu-cheow Lim
  • Patent number: 7379858
    Abstract: A Markov chain model of a software system may be used to compute all-pairs reaching probabilities to provide guidance in performing speculative operations with respect to the software system.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: Chu-Cheow Lim, Zhao Hui Du, Tin-Fook Ngai
  • Publication number: 20070157184
    Abstract: A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a shifting vector for the loop from the dependence equations group, wherein the shifting vector to represent an offset to apply to each statement in the loop for statement shifting. Other embodiments are also disclosed.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Li Liu, Zhaohui Du, Bu Cheng, Shiwei Liao, Gansha Wu, Tin-fook Ngai
  • Patent number: 7188234
    Abstract: A data processing apparatus, a computer, an article including a machine-accessible medium, and a method of processing data are disclosed. The data processing apparatus may include a pair of pipelines sharing an instruction cache, data cache, and a branch predictor with the second pipeline running ahead of the first pipeline using a data value prediction module. The pipelines may be included in one or more processors and coupled to a memory to form a computer. The method includes executing a plurality of instructions using the pipeline pair, such that when a cache miss is encountered by the second pipeline during execution of a LOAD instruction, the data value prediction module supplies a predicted load value in lieu of a cached value, enabling continued execution of the plurality of instructions by the second pipeline without waiting for the return of the cached value.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Tin-Fook Ngai
  • Patent number: 7181601
    Abstract: A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a speculative thread would execute desirably. The fork predictor may be implemented as a modified branch predictor circuit, and may have execution history updates entered by a determination of whether or not the execution of a speculative thread was or would have been desirable.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Kevin W. Rudd, Tin-Fook Ngai
  • Publication number: 20070011684
    Abstract: A method to optimize speculative parallel thread execution comprises selecting a plurality of partition candidate pairs for speculative parallel thread execution, transforming each partition candidate pair of the plurality of partition candidate pairs to improve the expected performance gain of each pair, and selecting a set of one or more transformed partition candidate pairs that do not interfere with each other and produce a maximum expected performance gain.
    Type: Application
    Filed: June 27, 2005
    Publication date: January 11, 2007
    Inventors: Zhao Du, Tin-fook Ngai, Chu-cheow Lim
  • Publication number: 20050223199
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Edward Grochowski, Hong Wang, John Shen, Perry Wang, Jamison Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Publication number: 20050198627
    Abstract: Sequential loops in computer programs may be identified and transformed into speculative parallel threads based on partitioning dependence graphs of sequential loops into pre-fork and post-fork regions.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 8, 2005
    Applicant: Intel Corporation
    Inventors: Zhao Du, Tin-Fook Ngai
  • Publication number: 20050182602
    Abstract: A Markov chain model of a software system may be used to compute all-pairs reaching probabilities to provide guidance in performing speculative operations with respect to the software system.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 18, 2005
    Applicant: Intel Corporation
    Inventors: Chu-Cheow Lim, Zhao Du, Tin-Fook Ngai