Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Abstract: The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

Abstract: The instant disclosure provides a gate device and an umbrella sharing system which utilizes the gate device. The gate device includes a base, an actuator, a pair of gate plates, and an identification sensor. The actuator is disposed on a top surface of the base and includes a latch extending downward through the base. The pair of gate plates are disposed on a bottom surface of the base, and each of the gate plates includes a guiding structure and a locking structure. A waiting zone for receiving an umbrella is defined between the two guiding structures. The latch of the actuator is driven to engage with the locking structures to limit the movement of the gate plates. The identification sensor is above the waiting zone and disposed on the base and is configured to identify the identity of an umbrella which enters the waiting zone.

Abstract: A semiconductor structure is provided. The semiconductor structure has a device region and a periphery region adjacent to the device region. The periphery region comprises an array contact defining region and a periphery contact defining region. The semiconductor structure comprises a substrate, a staircase structure, an etch stop layer, a plurality of array contacts, and a plurality of periphery contacts. The staircase structure is disposed on the substrate in the periphery region. The staircase structure comprises conductive layers and dielectric layers disposed alternately. The etch stop layer is disposed on the staircase structure in the array contact defining region. The array contacts are disposed on the staircase structure and through the etch stop layer in the array contact defining region. The periphery contacts are through the staircase structure in the periphery contact defining region.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: An electrical connector includes an insulating housing, a plurality of first terminals, a plurality of second terminals, a metal element and a fastening assembly. The insulating housing has a first insulating body, a second insulating body surrounding the first insulating body, a third insulating body and a fourth insulating body. The third insulating body is disposed to a rear end of a top surface of the first insulating body. The fourth insulating body is disposed to a top surface of the third insulating body. The plurality of the first terminals are surrounded by the first insulating body and the second insulating body. The plurality of the second terminals are surrounded by the third insulating body. The metal element is disposed to an outer surface of the insulating housing. The fastening assembly is positioned above the fourth insulating body.

Abstract: A semiconductor device includes a ground layer including a lower semiconductor material layer, a refilled semiconductor material layer disposed on the lower semiconductor material layer, and an upper conductive layer disposed on the refilled semiconductor material layer; a stacked structure disposed on the ground layer, including insulating layers and conductive layers alternately stacked along a first direction; and a conductive pillar penetrating the stacked structure and extending into the ground layer. The conductive pillar includes a bottom body portion corresponding to the ground layer, a middle body portion corresponding to middle and bottom portions of the stacked structure, and a plug. In a second direction, a first dimension in a portion of the bottom body portion overlapping the upper conductive layer is greater than a second dimension in a portion of the middle body portion overlapping a bottommost insulating layer of the stacked structure.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a stack, active structures connecting structures and isolation layers. The stack is disposed on the substrate. The active structures penetrate through the stack in sub-array regions thereof. A plurality of memory cells are defined by cross points of gate electrodes in the stack and the active structures. The connecting structures penetrate through the stack between the sub-array regions. Each connecting structure includes a first portion, a second portion and a third portion. The first portion is formed as an outermost layer of the connecting structure and formed of polysilicon. The second portion is disposed in a space defined by the first portion and formed of amorphous silicon. The third portion is disposed on the second portion and formed of amorphous silicon. The isolation layers are disposed between sidewalls of the stack and the connecting structures.

Abstract: An electrical connector includes an insulating body, a plurality of first terminals and a plurality of second terminals. The insulating body includes a first insulating body, a second insulating body and a third insulating body. A rear end of the first insulating body has an accommodating groove. The first insulating body has a plurality of first terminal grooves. The second insulating body is mounted in the accommodating groove. Several portions of a top surface of the second insulating body are recessed downward to form a plurality of second terminal grooves. The third insulating body is mounted on a lower portion of the rear of the second insulating body. The plurality of the first terminals are mounted in the plurality of the first terminal grooves. The plurality of the second terminals are mounted in the plurality of the second terminal grooves.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a conductive pillar having a sidewall and a multi-layer isolation structure on the sidewall of the conductive pillar. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive pillar and the second isolation layer. The first isolation layer includes protrusions extending toward the second isolation layer. A density of the first isolation layer is different from that of the second isolation layer.

Abstract: A waterproof socket connector includes an inner insulator, a plurality of terminals fastened in the inner insulator, at least one resistor, a conductive element, a grounding element, a shell, a sealing element and an outer insulator. The plurality of the terminals are a plurality of charging terminals and detection terminals. The at least one resistor is mounted to the detection terminals. The charging terminals are connected to the conductive element. The detection terminals are connected to the grounding element. The charging terminals are connected to the grounding element. The shell surrounds the inner insulator. A rear end of the shell is hollow to form an inner space. The sealing element is filled in the inner space. The outer insulator surrounds the inner insulator, the plurality of the terminals, the shell, the sealing element, the at least one resistor, the conductive element and grounding element.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region includes a plurality of complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an insulating layer on the N-type doped poly silicon layer; and a P-type doped poly silicon layer on the insulating layer. The array region includes a plurality of gate structures and a plurality of oxide layers alternately stacked on the P-type doped poly silicon layer, wherein a bottommost gate structure of the gate structures and the P-type doped poly silicon layer together serve as a plurality ground select lines of the semiconductor device. The array region further includes a vertical channel structure penetrating the gate structures and the oxide layers and extending into the N-type doped poly silicon layer.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor are provided. The semiconductor structure includes a channel pillar, a dielectric layer formed on the channel pillar, a via formed in the dielectric layer and electrically connected to the channel pillar, and a spacer formed between the dielectric layer and the via.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Abstract: A waterproof socket connector includes an inner insulator, a plurality of terminals fastened in the inner insulator, at least one resistor, a conductive element, a grounding element, a shell, a sealing element and an outer insulator. The plurality of the terminals are a plurality of charging terminals and detection terminals. The at least one resistor is mounted to the detection terminals. The charging terminals are connected to the conductive element. The detection terminals are connected to the grounding element. The charging terminals are connected to the grounding element. The shell surrounds the inner insulator. A rear end of the shell is hollow to form an inner space. The sealing element is filled in the inner space. The outer insulator surrounds the inner insulator, the plurality of the terminals, the shell, the sealing element, the at least one resistor, the conductive element and grounding element.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.