Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

Abstract: The present disclosure relates to an integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

Abstract: A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.

Abstract: An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger has a second height less than the first height.

Abstract: A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) device in which a slit at a movable mass of the MEMS device has a top notch slit profile. The MEMS device may, for example, be a speaker, an actuator, or the like. The slit extends through the movable mass, from top to bottom, and has a width that is uniform, or substantially uniform, from the bottom of the movable mass to proximate the top of movable mass. Further, in accordance with the top notch slit profile, top corner portions of the MEMS substrate in the slit are notched, such that a width of the slit bulges at the top of the movable mass. The top notch slit profile may, for example, increase the process window for removing an adhesive from the slit while forming the MEMS device.

Abstract: The present disclosure relates integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

Abstract: In accordance with some embodiments, a method of forming an auto-focusing device is provided. The method includes forming a cantilever beam member. The cantilever beam member has a ring shape. The method further includes forming a piezoelectric member over the cantilever beam member. The method also includes forming a membrane over the cantilever beam member. The membrane has a first region and a second region. The first region has a planar surface, and the second region is located between the first region and an inner edge of the cantilever beam member and has a plurality of corrugation structures. In addition, the method includes applying a liquid optical medium over the membrane and sealing the liquid optical medium with a protection layer.

Abstract: An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger and has a second height less than the first height.

Abstract: A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a substrate. A cavity is disposed in the substrate. A microelectromechanical system (MEMS) layer is disposed over the substrate. The MEMS layer comprises a movable diaphragm disposed over the cavity. The movable diaphragm comprises a central region and a peripheral region. The movable diaphragm is flat in the central region of the movable diaphragm. The movable diaphragm is corrugated in the peripheral region of the movable diaphragm.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a piezoelectric device including a piezoelectric membrane and a plurality of conductive layers. The method includes forming the plurality of conductive layers in the piezoelectric membrane, the plurality of conductive layers are vertically offset one another. A masking layer is formed over the piezoelectric membrane. An etch process is performed according to the masking layer to concurrently expose an upper surface of each conductive layer in the plurality of conductive layers. A plurality of conductive vias are formed over the upper surface of the plurality of conductive layers.

Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of layers on a base piezoelectric layer. The stack of layers includes a base metal film over the base piezoelectric layer; a first piezoelectric film over the base metal film; and a first metal film having an opening therein over the first piezoelectric film. The method also includes forming a trench in the stack of layers, wherein the trench passes through the opening in the first metal film but does not expose the base metal film; after forming the trench, forming a spacer structure under the first metal film but spaced apart from the base metal film; after forming the spacer structure, deepening the trench to expose the base metal film; and forming a contact in the trench.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a piezoelectric membrane overlying a substrate. A plurality of conductive layers is disposed within the piezoelectric membrane. The plurality of conductive layers comprises a first conductive layer over a second conductive layer. The first conductive layer comprises a first electrode and the second conductive layer comprises a second electrode. A first conductive via is disposed in the piezoelectric membrane and contacts the first electrode. A second conductive via is disposed in the piezoelectric membrane and contacts the second electrode. A sidewall of the second conductive via comprises a vertical sidewall segment overlying a slanted sidewall segment.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.

Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of piezoelectric films and metal films on a base layer, wherein the piezoelectric films and the metal films are arranged in an alternating manner. The method also includes forming a first trench in the stack of the piezoelectric films and the metal films. The method further includes forming at least one void at the side wall of the first trench. In addition, the method includes forming a spacer structure in the at least one void. The method further includes forming a contact in the first trench after the formation of the spacer structure.

Abstract: A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.

Abstract: Various embodiments of the present disclosure are directed towards a method to roughen a crystalline layer. A crystalline layer is deposited over a substrate. A mask material is diffused into the crystalline layer along grain boundaries of the crystalline layer. The crystalline layer and the mask material may, for example, respectively be or comprise polysilicon and silicon oxide. Other suitable materials are, however, amenable. An etch is performed into the crystalline layer with an etchant having a high selectivity for the crystalline layer relative to the mask material. The mask material defines micro masks embedded in the crystalline layer along the grain boundaries. The micro masks protect underlying portions of the crystalline layer during the etch, such that the etch forms trenches in the crystalline layer where unmasked by the micro masks.

Abstract: An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger and has a second height less than the first height.

Abstract: Various embodiments of the present disclosure are directed towards a method to roughen a crystalline layer. A crystalline layer is deposited over a substrate. A mask material is diffused into the crystalline layer along grain boundaries of the crystalline layer. The crystalline layer and the mask material may, for example, respectively be or comprise polysilicon and silicon oxide. Other suitable materials are, however, amenable. An etch is performed into the crystalline layer with an etchant having a high selectivity for the crystalline layer relative to the mask material. The mask material defines micro masks embedded in the crystalline layer along the grain boundaries. The micro masks protect underlying portions of the crystalline layer during the etch, such that the etch forms trenches in the crystalline layer where unmasked by the micro masks.