Patents by Inventor Ting-Yeh WU

Ting-Yeh WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658046
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: May 23, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ting-Yeh Wu
  • Patent number: 11587808
    Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: February 21, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ying-Lin Chen, Ting-Yeh Wu
  • Patent number: 11410945
    Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 9, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-Tou Tseng, Kun-Chi Hsu, Chin-Ta Wu, Ying-Lin Chen, Ting-Yeh Wu
  • Publication number: 20210288003
    Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.
    Type: Application
    Filed: November 10, 2020
    Publication date: September 16, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ying-Lin CHEN, Ting-Yeh WU
  • Publication number: 20210217632
    Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.
    Type: Application
    Filed: November 10, 2020
    Publication date: July 15, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ting-Yeh WU
  • Publication number: 20210217641
    Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.
    Type: Application
    Filed: August 20, 2020
    Publication date: July 15, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shih-Chun CHEN, Sheng-Tou TSENG, Kun-Chi HSU, Chin-Ta WU, Ying-Lin CHEN, Ting-Yeh WU