Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.

Abstract: In an array substrate, an electronic paper display panel and a drive method thereof, and a display device, a display area includes multiple sub-display areas. A plurality of scanning lines in each sub-display area are electrically insulated from each other, corresponding scanning lines in different sub-display areas are electrically connected to each other and display time of each sub-display area is controlled through control signal lines. When a control chip and a flexible circuit board are employed, only a small number of control chips and/or flexible circuit boards, or even only one control chip and/or one flexible circuit board, may drive multiple sub-display areas to display pictures.

Abstract: A phase shifter and a manufacturing method thereof and an antenna and a manufacturing method thereof are provided. The phase shifter includes: first and second substrates opposite to each other; a first electrode provided on the first substrate and configured to receive a ground signal; a second electrode provided on a side of the second substrate facing towards the first substrate; liquid crystals encapsulated between the first substrate and the second substrate and driven by the first electrode and the second electrode to rotate; and a support structure provided between the first substrate and the second substrate and including a first spacer. The first spacer is located on a side of the second electrode facing away from the second substrate, and an orthographic projection of the first spacer on the second substrate is within an orthographic projection of the second electrode on the second substrate.

Abstract: A phased-array antenna and a method for controlling the same are provided. The phased-array antenna includes first and second substrates between which a cavity is formed. Phase-shifting units in the cavity each includes: a power feeder located on a surface of the first substrate facing away from the second substrate and connected to a radio-frequency signal terminal, a radiator located on the surface and insulated from the power feeder, a ground electrode located on a surface of the first substrate facing towards the second substrate. The ground electrode connects to the ground signal terminal and overlaps with the power feeder and the radiator and includes a first and a second openings. A transmission electrode located on a surface of the second substrate facing the first substrate and connects to the control signal line.

Abstract: Chip package method and chip package structure are provided. The chip package method includes: providing a transparent substrate including a first side and a second side; coating the first side of the transparent substrate with an organic polymer material layer; depositing a protective layer on the organic polymer material layer; forming alignment parts on the protective layer; attaching a plurality of chips including metal pins; forming an encapsulating layer on the protective layer; polishing the encapsulating layer to expose the metal pins; forming a first insulating layer; forming first through holes in the first insulating layer; forming metal parts extending along sidewalls of the first through holes; and irradiating the second side of the transparent substrate by a laser to lift off the transparent substrate. The metal parts are insulated from each other and electrically connected to the metal pins.

Abstract: A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes exposes one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.

Abstract: Fingerprint recognition circuit, fingerprint recognition structure, fingerprint recognition device, display panel, and display device are provided. The circuit includes: a fingerprint recognition driving transistor; a first capacitor; a driving signal input terminal; and a sensing signal output terminal. The first capacitor has a terminal electrically connected to a gate of the fingerprint recognition driving transistor and another terminal electrically connected to a ground. The driving signal input terminal is electrically connected to an input terminal of the fingerprint recognition driving transistor. An output terminal of the fingerprint recognition driving transistor is electrically connected to the sensing signal output terminal.

Abstract: A panel includes a substrate, an array layer and an electrode array layer. The array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer. The substrate includes drive units arranged in an array, scan line groups, data lines extending in a second direction; and common signal lines extending in the second direction. The scan line group includes first scan lines and second scan lines, extending in a first direction. The first direction is perpendicular with the second direction. The electrode array layer includes drive electrodes arranged in an array; the drive electrodes correspond to the drive units; and the drive unit includes a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor.

Abstract: A phased-array antenna and a method for controlling the same are provided. The phased-array antenna includes first and second substrates between which a cavity is formed. Phase-shifting units in the cavity each includes: a power feeder located on a surface of the first substrate facing away from the second substrate and connected to a radio-frequency signal terminal, a radiator located on the surface and insulated from the power feeder, a ground electrode located on a surface of the first substrate facing towards the second substrate. The ground electrode connects to the ground signal terminal and overlaps with the power feeder and the radiator and includes a first and a second openings. A transmission electrode located on a surface of the second substrate facing the first substrate and connects to the control signal line.

Abstract: Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A microfluidic chip, a method for driving a microfluidic chip and an analysis apparatus are provided. An exemplary microfluidic chip includes a substrate; a number of M driving electrodes disposed on a side of the substrate and arranged along a first direction; and a number of N signal terminals electrically connected to the number of M driving electrodes. Any three adjacent driving electrodes are connected to different signal terminals, respectively; a number of A of the number of M driving electrodes are connected to a same signal terminal; and M, N and A are positive integers, and M?4, N?3, M>N, and A?2.

Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal, which are electrically connected with each other. The step-up unit includes a first module, a second module, a third module and a first capacitor, which are electrically connected with each other. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor. The third module is configured to transmit a signal of the third signal input terminal to the second electrode of the first capacitor, which further increases the signal of the first electrode of the first capacitor.

Abstract: The present disclosure provides a phased-array antenna and a control method thereof. The phased-array antenna includes two parallel substrates attached by sealant into a cavity filled with liquid crystals, a plurality of phase-shifting units is provided in the cavity defined. Each unit comprises: a power feeder electrically connected to a radio frequency signal terminal, a radiator electrically connected to the power feeder, a ground electrode electrically connected to a ground signal terminal but electrically insulated from the power feeder and the radiator respectively, and a driving electrode electrically connected to a control signal wire. The orthographic projections of the driving electrode, the power feeder, and the ground electrode overlap on one substrate.

Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A 3D printed display panel includes two opposing substrates and a black matrix formed on one of the substrates. The light proof areas of the black matrix include multiple first portions, multiple second portions and multiple third portions arranged to form a grid structure. The first portions and the third portions are alternately arranged in a direction of the scanning lines, the second portions and the third portions are alternately arranged in a direction of the data lines. Meshes of the grid structure are aperture zones of the black matrix. The aperture zones are in one-to-one correspondence with the pixel units. A vertical projections of the scanning lines and the data lines on the second substrate are located in the lightproof areas; where a minimum width of one first portion is X, a minimum width of one second portion is Y, and |X?Y|?2 ?m.

Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal, which are electrically connected with each other. The step-up unit includes a first module, a second module, a third module and a first capacitor, which are electrically connected with each other. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor. The third module is configured to transmit a signal of the third signal input terminal to the second electrode of the first capacitor, which further increases the signal of the first electrode of the first capacitor.

Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal. The step-up unit includes a first module, a second module and a first capacitor. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor at a first time period which generates a voltage difference between two electrodes of the first capacitor, and to transmit the signal of the fourth signal input terminal to the second electrode of the first capacitor at a second time period which further increases a signal of the first electrode of the first capacitor.

Abstract: A microfluidic chip, a method for driving a microfluidic chip and an analysis apparatus are provided. An exemplary microfluidic chip includes a substrate; a number of M driving electrodes disposed on a side of the substrate and arranged along a first direction; and a number of N signal terminals electrically connected to the number of M driving electrodes. Any three adjacent driving electrodes are connected to different signal terminals, respectively; a number of A of the number of M driving electrodes are connected to a same signal terminal; and M, N and A are positive integers, and M?4, N?3, M>N, and A?2.