Tod D. Wolf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A programmable, reconfigurable Reed-Solomon encoder/decoder allows for flexible reprogramming of encoders and decoders for a variety of applications. The standard Reed-Solomon parameters of the Galois Field order, the primitive polynomial, the number of symbols for each codeword of the transmitted and source data are settable via writable registers. The Reed-Solomon encoder/decoder may be coupled to a digital signal processor which specifies the parameters loaded in the writable registers via data register space of data memory space. The decoder and encoder parameters are separately specified and the decoder and encoder can run simultaneously and independently.
Abstract: An implementation of a multi-dimensional galois field multiplier and a method of galois field multi-dimensional multiplication which are able to support many communication standards having various symbol sizes(16), different GFs(14), and different primitive polynomials(12), in a cost-efficient manner is disclosed. The key to allow a single implementation to perform for all different GF sizes is to shift the one of the two operands(16) and primitive polynomial(12) to the left and to shift the intermediate output ZO(28) to the right in dependence upon the relative size of the GF(14) as compared to the size of the operand, primitive polynomial or intermediate output, whichever is being shifted. The shifting of the above-mentioned signals allows the MULT-XOR arrays(26) to operate on all fields with the exact same hardware with a minimum delay of 2 gates per block or with a critical delay of 2 XOR gates.
March 20, 1998
Date of Patent:
April 2, 2002
Texas Instruments Incorporated
Tod D. Wolf, Patrick W. Bosshart, David R. Shoemaker
Abstract: A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a signal-to-noise ratio based on the mean and variance of soft-output estimates. The decoding process is aborted based on a comparison of the generated signal-to-noise ratio to a predetermined threshold.
Abstract: The preferred embodiments generalize the Band Edge Component Maximization (BECM) timing recovery method and provide blind timing recovery in Quadrature Amplitude Modulation (QAM) using all the available information rather than sampling the BECM output at the symbol rate.
Abstract: A programmable logic device (130) as may be used in a communication system device such as a digital subscriber line modem (408) to perform Reed-Solomon decoding upon a received frame of digital values is disclosed. The programmable logic device (130) may be implemented as a DSP (130) or a general purpose microprocessor, for example. According to one disclosed embodiment of the invention, a group of look-up tables (60) are arranged, each look-up table (60) associated with one of the possible power values of a finite field, number up to twice the number of correctable errors. The contents of each entry (SYN) of the look-up tables (60) correspond to the finite field (e.g., Galois field) multiplication of a primitive element raised to an index power with a character of the finite field alphabet. Galois field multiplications (62) in syndrome accumulation may now be performed with a single table look-up operation.
Abstract: A programmable logic device, such as a digital signal processor (DSP) (130), having a Chien search unit (116) is disclosed. The Chien search unit (116) is arranged to perform finite field arithmetic functions useful in identifying roots of a polynomial, as is useful in Reed-Solomon decoding, particularly, after the execution of a Euclidean array function. Galois field multipliers (306) perform finite field multiplication of coefficient values (&Lgr;) and powers of symbol values (&agr;); the products of such multiplications are written into the coefficient register (304) for use in connection with the next symbol value. Finite field adders (308, 310; 318, 320) produce a final sum that is interrogated by zero detection circuitry (206) to determine whether a root is presented by the current symbol value.
Abstract: A combined Chien search and error position circuit (116), for use in Reed-Solomon decoding, is disclosed. The circuit (116) operates in response to a zero signal (ZRO) issued by a root detection block (200) that iteratively evaluates an error locator polynomial .LAMBDA.(x) over the Galois field used in the coding. A zeroes register (218) and a position register (22) are provided, each of which have a plurality of stages (218.sub.0 through 218.sub.t ; 220.sub.0 through 220.sub.t). An index counter (208) maintains a count over the Galois field, corresponding to the Galois field element under evaluation in the root detection block (200). An exponentiation circuit (212) performs a Galois field exponentiation of the count, and applies the result to the inputs of each of the zeroes register stages (218.sub.0 through 218.sub.t); the count is subtracted from the maximum Galois field index (e.g.
Abstract: The present invention represents Galois Field elements using power representation, rather than polynomial representation. Such representation eliminates the need for logarithm operations. It provides a simplified decoder and reduced critical path. Utilizing power notation to present field elements, the inventive implementation with modest support circuitry. Addition is more complicated but has a shorter critical path than the multiplication circuit for the polynomial filed element presentation.
Abstract: A programmable logic device, such as a digital signal processor (DSP) (130), having a Euclidean array unit (115; 115') is disclosed. The Euclidean array unit (115; 115') is arranged to perform finite field arithmetic functions useful in determining the greatest common factor among two polynomial series, in a sequential fashion beginning with a highest order pair of operands (A.sub.0, B.sub.0) and proceeding along the sequence. A source register (SRC) receives each pair of operands, and the results are stored in a result register (RES) in reverse order, prior to writing the results in memory. As a result, B result values are stored in the same location as the A input operand, and vice versa. This reversal of memory locations permits successive passes of the Euclidean operation to be carried out with simple incrementing of the starting byte address (SBA) at which the operands are located in memory, thus eliminating the need for large memory shifts.