Patents by Inventor Todd C. Roggenbauer
Todd C. Roggenbauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9397233Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).Type: GrantFiled: June 2, 2010Date of Patent: July 19, 2016Assignee: North Star Innovations Inc.Inventors: Ronghua Zhu, Vishnu Khemka, Amitava Bose, Todd C. Roggenbauer
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Patent number: 9142607Abstract: A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar.Type: GrantFiled: February 23, 2012Date of Patent: September 22, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Xu Cheng, Todd C. Roggenbauer, Jiang-Kai Zuo
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Publication number: 20130285201Abstract: Metal-insulator metal (MIM) capacitors are formed by providing a substrate having a first surface, forming thereon a first electrode having conductive and insulating regions wherein the conductive regions desirably have an area density DA less than 100%. A first dielectric is formed over the first electrode. A cavity is formed in the first dielectric, having a sidewall extending to the first electrode and exposing thereon some of the first electrode conductive and insulating regions. An electrically conductive barrier layer is formed covering the sidewall and the some of the first electrode conductive and insulating regions. A capacitor dielectric layer is formed in the cavity covering the barrier layer. A counter electrode is formed in the cavity covering the capacitor dielectric layer. External connections are formed to a portion of the first electrode laterally outside the cavity and to the counter electrode within the cavity.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Zhihong Zhang, Xu Cheng, Todd C. Roggenbauer, Jiang-Kai Zuo
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Publication number: 20130221482Abstract: A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xu Cheng, Todd C. Roggenbauer, Jiang-Kai Zuo
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Patent number: 8188543Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.Type: GrantFiled: November 3, 2006Date of Patent: May 29, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang
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Patent number: 7851857Abstract: A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.Type: GrantFiled: July 30, 2008Date of Patent: December 14, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Yue Fu, Ronghua Zhu, Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer
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Patent number: 7851889Abstract: Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well.Type: GrantFiled: April 30, 2007Date of Patent: December 14, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
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Patent number: 7820519Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.Type: GrantFiled: November 3, 2006Date of Patent: October 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang, Van Wong
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Publication number: 20100230736Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).Type: ApplicationFiled: June 2, 2010Publication date: September 16, 2010Inventors: Ronghua Zhu, Vishnu Khemka, Amitava Bose, Todd C. Roggenbauer
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Patent number: 7777257Abstract: A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed ends of the N regions (32, 52, 103) are terminated by N+ layers (31, 51, 131). Silicide layers (24, 34, 44, 54, 134, 124) are provided in contact with both ends of the parallel N and P regions (22, 32, 42, 52, 100, 103), thereby forming at the first end ohmic contacts (28, 48) with the P+ regions (21, 41, 121) and Schottky contacts (37, 57) with the N regions 32, 52, 103) and at the second, opposite end, ohmic contacts (38, 58) with the N+ regions (31, 51, 131) and Schottky contacts (27, 47) with the P regions (22, 42, 100). When forward biased current flows in both N (32, 52) and P (22, 42) regions thereby reducing the forward drop.Type: GrantFiled: February 14, 2007Date of Patent: August 17, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
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Patent number: 7763937Abstract: Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).Type: GrantFiled: November 15, 2006Date of Patent: July 27, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
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Patent number: 7732274Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).Type: GrantFiled: May 23, 2007Date of Patent: June 8, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Ronghua Zhu, Vishnu Khemka, Amitava Bose, Todd C. Roggenbauer
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Patent number: 7723204Abstract: A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive plates (106) may be formed over the first and second opposing inner walls (74, 76) of the isolation trench (62) respectively such that there is a gap (90) between the first and second conductive plates (106). First and second semiconductor devices (114) may be formed in the semiconductor substrate on opposing sides of the isolation trench (62). The method may include forming a trench (62) in a semiconductor substrate, forming first and second conductive plates (106) within the trench, and forming first and second semiconductor devices (114) in the semiconductor substrate on opposing sides of the trench (62).Type: GrantFiled: March 27, 2006Date of Patent: May 25, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
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Publication number: 20100025756Abstract: A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Inventors: Yue Fu, Ronghua Zhu, Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer
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Patent number: 7550804Abstract: A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).Type: GrantFiled: March 27, 2006Date of Patent: June 23, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
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Patent number: 7511319Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.Type: GrantFiled: February 24, 2006Date of Patent: March 31, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
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Publication number: 20080293211Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).Type: ApplicationFiled: May 23, 2007Publication date: November 27, 2008Inventors: Ronghua Zhu, Vishnu Khemka, Amitava Bose, Todd C. Roggenbauer
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Publication number: 20080265291Abstract: Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
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Patent number: 7439584Abstract: Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices.Type: GrantFiled: February 28, 2006Date of Patent: October 21, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer, Ronghua Zhu
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Patent number: 7436025Abstract: A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24? of the second dopant type.Type: GrantFiled: September 29, 2006Date of Patent: October 14, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer