Patents by Inventor Tofizur RAHMAN

Tofizur RAHMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10636960
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz
  • Publication number: 20200105324
    Abstract: A magnetic tunnel junction (MTJ) for use in a magnetic spin orbit torque random access memory device (SOT MRAM) is described. Magnetic tunnel junctions described herein include a multi-magnet free layer over a spin orbit torque electrode. The multi-magnet free layer includes at least three sub-layers: a first magnetic sub-layer in direct contact with the SOT electrode having a first magnetic stability, a second magnetic sub-layer having a second magnetic stability greater than the first magnetic stability, and a magnetic coupling layer between the first and second sub-layers.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Angeline Smith, Sasikanth Manipatruni, MD Tofizur Rahman, Noriyuki Sato, Tanay Gasovi, Christopher Wiegand, Ian Young
  • Publication number: 20200105998
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Angeline SMITH, Sasikanth MANIPATRUNI, Christopher WIEGAND, Tofizur RAHMAN, Noriyuki SATO, Benjamin BUFORD
  • Patent number: 10580970
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular MTJ material stacks with free magnetic layers are magnetically coupled through a metal material layer for improved stability and low damping. In some advantageous embodiments, layers of a free magnetic material stack are magnetically coupled through a coupling layer of a metal comprising at least molybdenum (Mo). The Mo may be in pure form or alloyed with other constituents.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10559744
    Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Brian Maertz, Christopher J. Wiegand, Daniel G. Oeullette, Md Tofizur Rahman, Oleg Golonzka, Justin S. Brockman, Tahir Ghani, Brian S. Doyle, Kevin P. O'Brien, Mark L. Doczy, Kaan Oguz
  • Publication number: 20200006424
    Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Tofizur Rahman, Gary Allen, Atm G. Sarwar, Ian Young, Hui Jae Yoo, Christopher Weigand, Benjamin Buford
  • Publication number: 20200006630
    Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki Sato, Tanay Gosavi, Gary Allen, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young, Ben Buford
  • Publication number: 20200006634
    Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Justin Brockman, Conor Puls, Stephen Wu, Christopher Wiegand, Tofizur Rahman, Daniel Ouellette, Angeline Smith, Andrew Smith, Pedro Quintero, Juan Alzate-Vinasco, Oleg Golonzka
  • Publication number: 20200006632
    Abstract: A memory device includes a bottom electrode, a conductive layer such as an alloy including ruthenium and tungsten above the bottom electrode and a perpendicular magnetic tunnel junction (pMTJ) on the conductive layer. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet on the tunnel barrier. The memory device further includes a synthetic antiferromagnetic (SAF) structure that is ferromagnetically coupled with the fixed magnet to pin a magnetization of the fixed magnet. The conductive layer has a crystal texture which promotes high quality FCC <111> crystal texture in the SAF structure and improves perpendicular magnetic anisotropy of the fixed magnet.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Daniel Ouellette, Justin Brockman, Tofizur Rahman, Angeline Smith, Andrew Smith, Christopher Wiegand, Oleg Golonzka
  • Publication number: 20200006631
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Noriyuki Sato, Tanay Gosavi, Justin Brockman, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • Publication number: 20200006635
    Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Tofizur Rahman, Christopher J. Wiegand, Justin S. Brockman, Daniel G. Ouellette, Angeline K. Smith, Andrew Smith, Pedro A. Quintero, Juan G. Alzate-Vinasco, Oleg Golonzka
  • Publication number: 20200006626
    Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Angeline Smith, Ian Young, Kaan Oguz, Sasikanth Manipatruni, Christopher Wiegand, Kevin O'Brien, Tofizur Rahman, Noriyuki Sato, Benjamin Buford, Tanay Gosavi
  • Publication number: 20200006637
    Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Tanay GOSAVI, Sasikanth MANIPATRUNI, Chia-Ching LIN, Kaan OGUZ, Christopher WIEGAND, Angeline SMITH, Noriyuki SATO, Kevin O'BRIEN, Benjamin BUFORD, Ian YOUNG, MD Tofizur RAHMAN
  • Publication number: 20190386205
    Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Noriyuki Sato, Kevin O'Brien, Benjamin Buford, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • Publication number: 20190386209
    Abstract: Material stacks for perpendicular spin transfer torque memory (pSTTM) devices, pSTTM devices and computing platforms employing such material stacks, and methods for forming them are discussed. The material stacks include a cladding layer of predominantly tungsten on a protective layer, which is in turn on an oxide capping layer over a magnetic junction stack. The cladding layer reduces oxygen dissociation from the oxide capping layer for improved thermal stability and retention.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Angeline Smith, Justin Brockman, Tofizur Rahman, Daniel Ouellette, Andrew Smith, Juan Alzate Vinasco, James ODonnell, Christopher Wiegand, Oleg Golonzka
  • Publication number: 20190378972
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 12, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190334079
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Application
    Filed: December 30, 2016
    Publication date: October 31, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Justin S. BROCKMAN, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190288190
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10418415
    Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Wiegand, Oleg Golonzka, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Kevin P. O'Brien, Kaan Oguz, Tahir Ghani, Satyarth Suri
  • Publication number: 20190280188
    Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: September 12, 2019
    Inventors: Justin BROCKMAN, Christopher WIEGAND, MD Tofizur RAHMAN, Daniel OUELETTE, Angeline SMITH, Juan ALZATE VINASCO, Charles KUO, Mark DOCZY, Kaan OGUZ, Kevin O'BRIEN, Brian DOYLE, Oleg GOLONZKA, Tahir GHANI