Patents by Inventor Tokuaki Kuniyoshi
Tokuaki Kuniyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11316061Abstract: n-type amorphous semiconductor layers (4) and p-type amorphous semiconductor layers (5) are alternately disposed on the back surface of a semiconductor substrate (1) so as to be separated from each other at a desired interval paralleled with the direction of the surface of the semiconductor substrate (1). An electrode (6) is disposed on the n-type amorphous semiconductor layer (4), and an electrode (7) is disposed on the p-type amorphous semiconductor layer (5). A protective film (8) includes an insulating film, and is disposed on a passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7), so as to be in contact with the passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7).Type: GrantFiled: October 15, 2020Date of Patent: April 26, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Tokuaki Kuniyoshi, Liumin Zou
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Patent number: 11227966Abstract: Provided is a photoelectric conversion device capable of suppressing diffusion of a dopant in a p layer or n layer into an adjacent layer. A photoelectric conversion device is provided with a silicon substrate, a substantially intrinsic amorphous layer formed on one surface of the silicon substrate, and a first conductive amorphous layer that is formed on the intrinsic amorphous layer. The first conductive amorphous layer includes a first concentration layer and a second concentration layer that is stacked on the first concentration layer. The dopant concentration of the second concentration layer is 8×1017 cm?3 or more, and is lower than the dopant concentration of the first concentration layer.Type: GrantFiled: April 3, 2015Date of Patent: January 18, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Masatomi Harada, Toshihiko Sakai, Rihito Suganuma, Kazuya Tsujino, Tokuaki Kuniyoshi, Takeshi Kamikawa
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Publication number: 20210050467Abstract: n-type amorphous semiconductor layers (4) and p-type amorphous semiconductor layers (5) are alternately disposed on the back surface of a semiconductor substrate (1) so as to be separated from each other at a desired interval paralleled with the direction of the surface of the semiconductor substrate (1). An electrode (6) is disposed on the n-type amorphous semiconductor layer (4), and an electrode (7) is disposed on the p-type amorphous semiconductor layer (5). A protective film (8) includes an insulating film, and is disposed on a passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7), so as to be in contact with the passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7).Type: ApplicationFiled: October 15, 2020Publication date: February 18, 2021Inventors: Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Tokuaki Kuniyoshi, Liumin Zou
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Patent number: 10879329Abstract: A semiconductor device includes a base, a first wiring line, a semiconductor film, a second wiring line, an insulating film, and a semiconductor auxiliary layer. The first wiring line is provided in the first, second, and third regions of the base. The semiconductor film has one or more low-resistance regions, is provided between the first wiring line and the base in the first region, and is in contact with the first wiring line in the second region. The second wiring line is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region. The semiconductor auxiliary layer is in contact with the semiconductor film at least in the first region, and assists electrical coupling via the first region.Type: GrantFiled: February 12, 2019Date of Patent: December 29, 2020Assignee: JOLED INC.Inventors: Tokuaki Kuniyoshi, Naoki Asano, Ryo Koshiishi, Hiroshi Fujimura
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Patent number: 10879402Abstract: A thin film transistor includes a substrate, a semiconductor layer, a first gate insulating film, a second gate insulating film, and a gate electrode. The semiconductor layer is provided in a selective region of the substrate. The first gate insulating film is provided in the selective region of the substrate and covers a surface of the semiconductor layer. The second gate insulating film extends across opposite sides of the first gate insulating film along a channel width direction and covers the first gate insulating film that covers the semiconductor layer. The gate electrode faces the semiconductor layer across the second gate insulating film.Type: GrantFiled: October 3, 2018Date of Patent: December 29, 2020Assignee: JOLED INC.Inventors: Naoki Asano, Tokuaki Kuniyoshi
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Patent number: 10658526Abstract: In a photovoltaic device (1), first amorphous semiconductor portions (102n) and second amorphous semiconductor portions (102p) are provided alternately on one of faces of a semiconductor substrate (101). Each first amorphous semiconductor portion (102n) has at least one first amorphous semiconductor strip (1020n), and each second amorphous semiconductor portion (102p) has at least one second amorphous semiconductor strip (1020p). A plurality of first electrodes (103n) are provided spaced apart from each other on each first amorphous semiconductor strip (1020n), and a plurality of second electrodes (103p) are provided spaced apart from each other on each second amorphous semiconductor strip (1020p).Type: GrantFiled: February 24, 2016Date of Patent: May 19, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Masatomi Harada, Kenichi Higashi, Takeshi Kamikawa, Toshihiko Sakai, Tokuaki Kuniyoshi, Kazuya Tsujino, Liumin Zou
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Patent number: 10505064Abstract: A photovoltaic device and a photovoltaic module are provided that suppressing diffusion of boron and thereby improving conversion efficiency. A photovoltaic device 10 includes: a semiconductor substrate 1; an intrinsic amorphous semiconductor layer 3 provided on the semiconductor substrate 1; n-type amorphous semiconductor strips 4 containing phosphorus as a dopant; and p-type amorphous semiconductor strips 5 containing boron as a dopant, the n- and p-type amorphous semiconductor strips 4 and 5 being provided alternately on the intrinsic amorphous semiconductor layer 3 as viewed along an in-plane direction. Each n-type amorphous semiconductor strip 4 includes a reduced-thickness region TD(n) on a face thereof adjacent to one of the p-type amorphous semiconductor strips 5. Each p-type amorphous semiconductor strip 5 includes a reduced-thickness region TD(p) on a face thereof adjacent to one of the n-type amorphous semiconductor strips 4.Type: GrantFiled: August 30, 2016Date of Patent: December 10, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Tokuaki Kuniyoshi, Kenichi Higashi, Takeshi Kamikawa, Masatomi Harada, Toshihiko Sakai, Kazuya Tsujino, Liumin Zou
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Publication number: 20190305064Abstract: A semiconductor device includes a base, a first wiring line, a semiconductor film, a second wiring line, an insulating film, and a semiconductor auxiliary layer. The first wiring line is provided in the first, second, and third regions of the base. The semiconductor film has one or more low-resistance regions, is provided between the first wiring line and the base in the first region, and is in contact with the first wiring line in the second region. The second wiring line is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region. The semiconductor auxiliary layer is in contact with the semiconductor film at least in the first region, and assists electrical coupling via the first region.Type: ApplicationFiled: February 12, 2019Publication date: October 3, 2019Inventors: Tokuaki KUNIYOSHI, Naoki ASANO, Ryo KOSHIISHI, Hiroshi FUJIMURA
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Patent number: 10431603Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.Type: GrantFiled: January 5, 2018Date of Patent: October 1, 2019Assignee: JOLED INC.Inventors: Hiroshi Hayashi, Tokuaki Kuniyoshi, Yasuhiro Terai, Eri Matsuo, Toshiaki Yoshitani, Naoki Asano
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Publication number: 20190259878Abstract: A thin film transistor includes a substrate, a semiconductor layer, a first gate insulating film, a second gate insulating film, and a gate electrode. The semiconductor layer is provided in a selective region of the substrate. The first gate insulating film is provided in the selective region of the substrate and covers a surface of the semiconductor layer. The second gate insulating film extends across opposite sides of the first gate insulating film along a channel width direction and covers the first gate insulating film that covers the semiconductor layer. The gate electrode faces the semiconductor layer across the second gate insulating film.Type: ApplicationFiled: October 3, 2018Publication date: August 22, 2019Inventors: Naoki ASANO, Tokuaki KUNIYOSHI
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Patent number: 10355145Abstract: A photovoltaic device (1) includes: an i-type amorphous semiconductor layer (102i) formed in contact with one of the surfaces of a semiconductor substrate (101); p-type amorphous semiconductor strips (102p) spaced apart from each other and provided on the i-type amorphous semiconductor layer (102i); and n-type amorphous semiconductor strips (102n) spaced apart from each other and provided on the i amorphous semiconductor layer (102i), each n-type amorphous semiconductor strip (102n) being adjacent to at least one of the p-type amorphous semiconductor strips (102p) as traced along an in-plane direction of the semiconductor substrate (101). The photovoltaic device (1) further includes electrodes (103) as a protection layer formed in contact with the i-type amorphous semiconductor layer (102) between adjacent p-type amorphous semiconductor strips (102p) and between adjacent n-type amorphous semiconductor strips (102n).Type: GrantFiled: February 24, 2016Date of Patent: July 16, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Masatomi Harada, Kenichi Higashi, Takeshi Kamikawa, Toshihiko Sakai, Tokuaki Kuniyoshi, Kazuya Tsujino, Liumin Zou
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Patent number: 10293368Abstract: A film-forming method for forming a thin film on a substrate includes a contact step, an external force removal step, and a film-forming step. At the contact step (step B), the substrate 30 and a member 31 in contact with one surface of the substrate is stacked, and the substrate 30 and the member 31 in contact with one surface of the substrate are placed under vacuum while an external force is applied in a direction in which the substrate 30 and the member 31 in contact with one surface of the substrate are stacked. At the external force removal step (step C), the external force is removed at atmospheric pressure or under vacuum. At a film-forming step (step E), a thin film is formed on the one surface or the other surface of the substrate 30.Type: GrantFiled: February 24, 2016Date of Patent: May 21, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Toshihiko Sakai, Takeshi Kamikawa, Masatomi Harada, Tokuaki Kuniyoshi, Liumin Zou
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Publication number: 20190044018Abstract: A photovoltaic device and a photovoltaic module are provided that suppressing diffusion of boron and thereby improving conversion efficiency. A photovoltaic device 10 includes: a semiconductor substrate 1; an intrinsic amorphous semiconductor layer 3 provided on the semiconductor substrate 1; n-type amorphous semiconductor strips 4 containing phosphorus as a dopant; and p-type amorphous semiconductor strips 5 containing boron as a dopant, the n- and p-type amorphous semiconductor strips 4 and 5 being provided alternately on the intrinsic amorphous semiconductor layer 3 as viewed along an in-plane direction. Each n-type amorphous semiconductor strip 4 includes a reduced-thickness region TD(n) on a face thereof adjacent to one of the p-type amorphous semiconductor strips 5. Each p-type amorphous semiconductor strip 5 includes a reduced-thickness region TD(p) on a face thereof adjacent to one of the n-type amorphous semiconductor strips 4.Type: ApplicationFiled: August 30, 2016Publication date: February 7, 2019Applicant: Sharp Kabushiki KaishaInventors: Tokuaki KUNIYOSHI, Kenichi HIGASHI, Takeshi KAMIKAWA, Masatomi HARADA, Toshihiko SAKAI, Kazuya TSUJINO, Liumin ZOU
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Publication number: 20180197884Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.Type: ApplicationFiled: January 5, 2018Publication date: July 12, 2018Inventors: Hiroshi HAYASHI, Tokuaki KUNIYOSHI, Yasuhiro TERAI, Eri MATSUO, Toshiaki YOSHITANI, Naoki ASANO
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Publication number: 20180190840Abstract: In a photovoltaic device (1), first amorphous semiconductor portions (102n) and second amorphous semiconductor portions (102p) are provided alternately on one of faces of a semiconductor substrate (101). Each first amorphous semiconductor portion (102n) has at least one first amorphous semiconductor strip (1020n), and each second amorphous semiconductor portion (102p) has at least one second amorphous semiconductor strip (1020p). A plurality of first electrodes (103n) are provided spaced apart from each other on each first amorphous semiconductor strip (1020n), and a plurality of second electrodes (103p) are provided spaced apart from each other on each second amorphous semiconductor strip (1020p).Type: ApplicationFiled: February 24, 2016Publication date: July 5, 2018Applicant: Sharp Kabushiki KaishaInventors: MASATOMI HARADA, KENICHI HIGASHI, TAKESHI KAMIKAWA, TOSHIHIKO SAKAI, TOKUAKI KUNIYOSHI, KAZUYA TSUJINO, LIUMIN ZOU
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Publication number: 20180161808Abstract: A film-forming method for forming a thin film on a substrate includes a contact step, an external force removal step, and a film-forming step. At the contact step (step B), the substrate 30 and a member 31 in contact with one surface of the substrate is stacked, and the substrate 30 and the member 31 in contact with one surface of the substrate are placed under vacuum while an external force is applied in a direction in which the substrate 30 and the member 31 in contact with one surface of the substrate are stacked. At the external force removal step (step C), the external force is removed at atmospheric pressure or under vacuum. At a film-forming step (step E), a thin film is formed on the one surface or the other surface of the substrate 30.Type: ApplicationFiled: February 24, 2016Publication date: June 14, 2018Inventors: TOSHIHIKO SAKAI, TAKESHI KAMIKAWA, MASATOMI HARADA, TOKUAKI KUNIYOSHI, LIUMIN ZOU
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Publication number: 20180138323Abstract: A photovoltaic device (1) includes: an i-type amorphous semiconductor layer (102i) formed in contact with one of the surfaces of a semiconductor substrate (101); p-type amorphous semiconductor strips (102p) spaced apart from each other and provided on the i-type amorphous semiconductor layer (102i); and n-type amorphous semiconductor strips (102n) spaced apart from each other and provided on the i amorphous semiconductor layer (102i), each n-type amorphous semiconductor strip (102n) being adjacent to at least one of the p-type amorphous semiconductor strips (102p) as traced along an in-plane direction of the semiconductor substrate (101). The photovoltaic device (1) further includes electrodes (103) as a protection layer formed in contact with the i-type amorphous semiconductor layer (102) between adjacent p-type amorphous semiconductor strips (102) and between adjacent n-type amorphous semiconductor strips (102n).Type: ApplicationFiled: February 24, 2016Publication date: May 17, 2018Inventors: MASATOMI HARADA, KENICHI HIGASHI, TAKESHI KAMIKAWA, TOSHIHIKO SAKAI, TOKUAKI KUNIYOSHI, KAZUYA TSUJINO, LIUMIN ZOU
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Publication number: 20170338365Abstract: n-type amorphous semiconductor layers (4) and p-type amorphous semiconductor layers (5) are alternately disposed on the back surface of a semiconductor substrate (1) so as to be separated from each other at a desired interval paralleled with the direction of the surface of the semiconductor substrate (1). An electrode (6) is disposed on the n-type amorphous semiconductor layer (4), and an electrode (7) is disposed on the p-type amorphous semiconductor layer (5). A protective film (8) includes an insulating film, and is disposed on a passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7), so as to be in contact with the passivation film (3), the n-type amorphous semiconductor layer (4), the p-type amorphous semiconductor layer (5), and the electrodes (6, 7).Type: ApplicationFiled: October 23, 2015Publication date: November 23, 2017Applicant: Sharp Kabushiki KaishaInventors: TAKESHI KAMIKAWA, MASATOMI HARADA, TOSHIHIKO SAKAI, TOKUAKI KUNIYOSHI, LIUMIN ZOU
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Publication number: 20170033252Abstract: Provided is a photoelectric conversion device capable of suppressing diffusion of a dopant in a p layer or n layer into an adjacent layer. A photoelectric conversion device is provided with a silicon substrate, a substantially intrinsic amorphous layer formed on one surface of the silicon substrate, and a first conductive amorphous layer that is formed on the intrinsic amorphous layer. The first conductive amorphous layer includes a first concentration layer and a second concentration layer that is stacked on the first concentration layer. The dopant concentration of the second concentration layer is 8×1017 cm?3 or more, and is lower than the dopant concentration of the first concentration layer.Type: ApplicationFiled: April 3, 2015Publication date: February 2, 2017Inventors: Masatomi HARADA, Toshihiko SAKAI, Rihito SUGANUMA, Kazuya TSUJINO, Tokuaki KUNIYOSHI, Takeshi KAMIKAWA
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Publication number: 20160268462Abstract: A photoelectric conversion element 100 includes an n-type monocrystalline silicon substrate 1, an non-crystalline thin film 2, i-type non-crystalline thin films 11 to 1m and 21 to 2m?1, p-type non-crystalline thin films 31 to 3m, and n-type non-crystalline thin films 41 to 4m?1. The non-crystalline thin film 2 is configured of non-crystalline thin films 201 and 202 and is disposed in contact with the surface on the light incident side of the n-type monocrystalline silicon substrate 1. The non-crystalline thin film 201 is configured of a-Si, and the non-crystalline thin film 202 is configured of a-SiNx (0.78?x?1.03). The i-type non-crystalline thin films 11 to 1m and 21 to 2m?1 are disposed in contact with the rear surface of the n-type monocrystalline silicon substrate 1. The p-type non-crystalline thin films 31 to 3m are disposed in contact with the i-type non-crystalline thin films 11 to 1m.Type: ApplicationFiled: August 29, 2014Publication date: September 15, 2016Inventors: Kenji KIMOTO, Naoki KOIDE, Toshihiko SAKAI, Tokuaki KUNIYOSHI