Abstract: A policing technique for a telecommunications traffic of variable length packets is described. The technique uses a plurality of police engines, grouped in pairs. A selection module selects a police engine pair to process a packet. Each police engine contains a conformance unit, credit unit and a debit unit, in which the credit update of one police engine influences the credit update of the other police engine in the pair. The technique also uses a combinatorial function to decide on a category of a processed packet and which police engines to update their debit units.

Abstract: The method of buffering packets in a digital communications device includes defining an n-level hierarchy of memory partitions, wherein each non-top level partition has one or more child partitions at an immediately lower level of the hierarchy. The memory partitions at the top-most level are pre-configured with a target memory occupancy size, and the target occupancy for each memory partition situated at a lower level is recursively computed in a dynamic manner based on the aggregate congestion of its parent partition, until the target occupancies for the bottom-most memory partitions are determined. Each traffic flow which uses the buffer is associated with one of the memory partitions at the bottom-most level of the hierarchy and packet discard is enabled in the event the actual memory occupancy of a traffic flow exceeds its target occupancy.

Abstract: In an N×N packet switch, for example an ATM switch, multicast connections receive backpressure signals from congested output ports in the switch core. The cells in the connections are destination address modified not to send to the congested output port, but to continue sending to the other output ports in the connection. The multicast cells may include a user selected primary route identification and be queued in a unicast input queue for the primary route before being destination address modified. Destination address modification for congestion may be accompanied by partial packet discard, through destination address modification of the remaining cells forming part of a multiple cell packet to remove the destination address for the congested port (whether or not it is now congested) where one of the multiple destination addresses of one of the cells in the packet has been modified to remove the destination address of the congested output port.

Abstract: A packet processing device has an on-board match engine memory. Actions to be taken on a packet can be looked up in the match engine memory using a key comprising a match engine index and a protocol field from the packet. The match engine index is obtained from either a relatively small on-board parser memory or a larger context memory. The parser memory contains match engine indices for sparse protocols. Performance approaching that of hard-wired packet processors can be obtained. New protocols or changes in protocols can be accommodated by writing new values into the match engine, parser and context memories. The packet processing device can be provided in a pipelined architecture.

Abstract: The present invention provides improved methods for conducting living/controlled polymerization on polymeric solid supports. The improved methods allow polymerization to occur directly from the non-functionalized surface of a bulk support. In addition, polymerization may be re-initiated to provide co-polymers. The disclosed methods may employ the non-nitroxide-based RAFT and ATRP control agents that allow controlled polymerization to proceed at relatively low temperatures (<80° C.). Furthermore, these improved methods may provide graft polymers with decreased levels of “in-growth” of the bulk solid support. The invention also provides substrate polymers, with improved properties for solid phase synthesis and diagnostic applications, which may be made by the disclosed methods.

Abstract: A system and method for adaptively assigning queue service weights to an ATM traffic management controller in order to reduce service weight update calculations. The implementation of a fair weighted queuing scheme on a network is divided into two functions: queue arbitration; and queue weight configuration. Queue arbitration is performed via a virtual time-stamped fair queuing algorithm. The queue weight configuration is performed via a reconfigurable weighted fair queuing controller wherein bandwidth requirements are calculated in response to connection setup and release values.

Abstract: A product saver for facilitating the transfer of the contents of an upper most bottle to a cavity within a lower most bottle. The device includes a pair of fittings between which a butterfly valve is positioned such that the contents of the upper most bottle can settle against the butterfly valve which can then be opened and allowing the rapid transfer of the contents of the upper most bottle into the cavity of the lower most bottle.

Abstract: A system and method for adaptively assigning queue service weights to an ATM traffic management controller in order to reduce service weight update calculations. The implementation of a fair weighted queuing scheme on a network is divided into two functions: queue arbitration; and queue weight configuration. Queue arbitration is performed via a virtual time-stamped fair queuing algorithm. The queue weight configuration is performed via a reconfigurable weighted fair queuing controller wherein bandwidth requirements are calculated in response to connection setup and release values.

Abstract: A device and algorithm for fairly allocating available bandwidth between contending connections at a contention point in a data network. The allocation is based on global queue size at the contention point and a weighted value assigned to the data traffic. The device and algorithm find particular application in an ATM network which supports the available bit rate (ABR) service category.

Abstract: A scheduling device for use in a packet-switched network, belonging to the class of non-work conserving or idling weighted round robin (WRR) arbiters, assigns a packet stream slots in a fixed-length time division multiple access (TDMA) frame by selecting free slots which are closest to ideal slot positions that would, if assigned, eliminate jitter or cell delay variation. The scheduler is able to simultaneously determine if a new constant bit rate connection requiring a predetermined bandwidth conforms to a leaky bucket or GCRA algorithm characterized by a peak packet or cell emission interval T=1/PCR and a packet or cell delay variation time, CDVT, i.e., whether the new connection is GCRA (T, CDVT) conformant.

Abstract: A system and method for adaptively assigning queue service weights to an ATM traffic management controller in order to reduce service weight update calculations. The implementation of a fair weighted queuing scheme on a network is divided into two functions: queue arbitration; and queue weight configuration. Queue arbitration is performed via a virtual time-stamped fair queuing algorithm. The queue weight configuration is performed via a reconfigurable weighted fair queuing controller wherein bandwidth requirements are calculated in response to connection setup and release values.