Abstract: A wall surface of a reinforcing bracket is provided with engagement holes (engaged portions) on a front side and a rear side, respectively. A lower arm of a front door and a lower arm of a rear door are each provided with an engagement projection (engaging portion) that engages with an engagement hole when the front door and the rear door fully close.

Abstract: A semiconductor device with less variation in transistor characteristics is provided. The semiconductor device includes a semiconductor film, a pair of blocking films over the semiconductor film, and an insulating film provided over the semiconductor film and between the pair of blocking films. The semiconductor film includes a pair of n-type regions and an i-type region provided between the pair of n-type regions. The n-type regions overlap with the blocking films. The i-type region overlaps with the insulating film.

Abstract: A motor includes a rotor, a stator, and a circuit board below the stator. The stator includes an insulator to cover at least a portion of each of an upper surface, a lower surface, and circumferential side surfaces of each of teeth of the stator, coils each of which is defined by a conducting wire wound around a separate one of the teeth with the insulator therebetween, and a drawn-out wire drawn out from the coils and electrically connected to the circuit board. A lower portion of the insulator includes a guide radially outward of the coils and including a wall extending downward from a lower surface of the insulator and a bend extending radially outward from a lower end of the wall. At least a portion of the drawn-out wire extends in a circumferential direction along a radially outer surface of the wall.

Abstract: A vehicle sliding door, including: an outer panel; an inner panel; a module panel to which devices are fixed; a first reinforcement member for reinforcing a sliding-direction end portion of the inner panel; and a fixation part to which the inner panel, the module panel and the first reinforcement member are fixed is provided.

Abstract: A motor includes a rotor, a stator, and a circuit board below the stator. The stator includes an insulator to cover at least a portion of each of an upper surface, a lower surface, and circumferential side surfaces of each of teeth of the stator, coils each of which is defined by a conducting wire wound around a separate one of the teeth with the insulator therebetween, and a drawn-out wire drawn out from the coils and electrically connected to the circuit board. A lower portion of the insulator includes a guide radially outward of the coils and including a wall extending downward from a lower surface of the insulator and a bend extending radially outward from a lower end of the wall. At least a portion of the drawn-out wire extends in a circumferential direction along a radially outer surface of the wall.

Abstract: A processor includes a plurality of arithmetic and logic units configured to operate in parallel with one another and a first reduction circuit including a first adder configured to simultaneously add together a plurality of arithmetic results output from the plurality of arithmetic and logic units. Further, an arithmetic processing device includes a plurality of processors each including the plurality of arithmetic and logic units configured to operate in parallel with one another and a first reduction circuit including a first adder configured to simultaneously add together a plurality of arithmetic results output from the plurality of arithmetic and logic units.

Abstract: A motor includes a rotary portion including a shaft having a center on a vertically extending central axis. A bearing portion rotatably supports the shaft. A stationary portion includes a stator. The bearing portion is radially outward of the shaft and includes a sleeve bearing that contains a lubricating oil; and a housing radially outward of the sleeve bearing. The stator includes a stator core that is radially outward of the housing; and an insulator that covers at least part of the stator core. The insulator includes an upper insulating portion that covers an upper face of the stator core; a connecting portion that extends radially inward from the upper insulating portion; and an insulator inclined portion that is inclined in a direction away from the central axis, away from the connecting portion.

Abstract: A motor includes a rotary portion including a shaft with a central axis. A bearing portion is radially outward of and rotatably supporting the shaft. A stationary portion includes a stator including a stator core radially outward of the housing; and an insulator at least partially covering the stator core. The bearing portion includes a sleeve bearing containing a lubricating oil; and a housing radially outward of the sleeve bearing. The shaft holds a first member above the sleeve bearing and extending radially outward from the shaft. The housing holds a second member above the sleeve bearing and below the first member and extending radially inward from the housing. The first and second members face each other with a gap therebetween. The second member includes a first hole surrounding the shaft; and at least one second hole radially outward of the first hole.

Abstract: A vehicle sliding door, including: an outer panel; an inner panel; a module panel to which devices are fixed; a first reinforcement member for reinforcing a sliding-direction end portion of the inner panel; and a fixation part to which the inner panel, the module panel and the first reinforcement member are fixed is provided.

Abstract: The micro-molding equipment contains a preform molding equipment 10 taking a single-cavity of a preform material 3 corresponding to a small precision optical component to be molded with a runnerless mold, and a precision compression molding equipment 40 for after molding the preform material 3 by primary compression molding in a vacuum state, cooling the preform material to a temperature near a glass transition point, and then re-softening a surface layer of the preform material and molding the same by secondary compression molding to transfer the small precision optical component thereto.

Abstract: A DSP comprises pipeline registers, a logical operation circuit, a product-sum circuit, DSP registers and an interface. The DSP registers includes at least a plurality of program control registers and excludes the pipeline registers, the logical operation circuit, the product-sum circuit. The interface is connected to the DSP registers, and causes an external device to be capable of writing and reading out from the DSP registers.

Abstract: A DSP comprises pipeline registers, a logical operation circuit, a product-sum circuit, DSP registers and an interface. The DSP registers includes at least a plurality of program control registers and excludes the pipeline registers, the logical operation circuit, the product-sum circuit. The interface is connected to the DSP registers, and causes an external device to be capable of writing and reading out from the DSP registers.

Abstract: A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame.

Abstract: A data write circuit is interposed between a CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific address in the memory, and access mode designation data for designating one of a byte access mode, half-word access mode, and word access mode. The data write circuit comprises a decoder for decoding the access mode designation data, a logic circuit for generating selection signals, and four selectors, each of which deals with 8-bit data consisting of eight prescribed bits of the original thirty-two bits. Each selector selects either first data read from the memory or second data output from the CPU. Therefore, each selector is capable of selecting the second data, which are substituted for the first data in the memory. Thus, it is possible to perform write operations in desired units in the memory.

Abstract: A data write circuit is interposed between a CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific address in the memory, and access mode designation data for designating one of a byte access mode, half-word access mode, and word access mode. The data write circuit comprises a decoder for decoding the access mode designation data, a logic circuit for generating selection signals, and four selectors, each of which deals with 8-bit data consisting of eight prescribed bits of the original thirty-two bits. Each selector selects either first data read from the memory or second data output from the CPU. Therefore, each selector is capable of selecting the second data, which are substituted for the first data in the memory. Thus, it is possible to perform write operations in desired units in the memory.

Abstract: A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame.

Abstract: A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame.

Abstract: A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame.

Abstract: A control apparatus controls writing and reading of data with respect to a memory which is randomly accessible. An address producing device produces an address by a method according to a predetermined rule, in response to a request to access the memory by the method according to the predetermined rule. A switching device selects one of an address with which the memory is randomly accessed and the address produced by the address producing device. Data is written into and read from the memory, at a location that corresponds to the address that is selected by the switching device and supplied to the memory.